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͂pfmlib_ospfm_cfg__pfm_dbprintf__pfm_vbprintfpfmlib_getlpfmlib_strconcatpfmlib_compact_pattrspfmlib_check_structpfmlib_build_fstrpfm_initializepfm_terminatepfm_find_eventpfmlib_parse_eventpfmlib_release_eventpfm_strerrorpfm_get_versionpfm_get_event_nextpfm_get_os_event_encodingpfm_get_event_encodingpfm_pmu_validatepfm_get_event_infopfm_get_event_attr_infopfm_get_pmu_infopfmlib_get_pmu_by_typepfmlib_sort_attrperf_event_supportpfm_get_perf_event_encodingpfmlib_os_perfpfmlib_os_perf_extpfm_intel_x86_get_perf_encodingpfm_intel_nhm_unc_get_perf_encodingpfm_intel_x86_requesting_pebspfm_intel_x86_perf_validate_pattrspfm_intel_x86_perf_detectpfm_amd64_get_perf_encodingpfm_amd64_perf_validate_pattrspfm_netburst_get_perf_encodingpfm_netburst_perf_validate_pattrspfm_intel_snbep_unc_get_perf_encodingpfm_intel_snbep_unc_perf_validate_pattrsamd64_modsamd64_supportpfm_amd64_cfgamd64_display_regpfm_amd64_detectpfm_amd64_get_encodingpfm_amd64_get_event_firstpfm_amd64_get_event_nextpfm_amd64_event_is_validpfm_amd64_get_event_attr_infopfm_amd64_get_event_infopfm_amd64_validate_tablepfm_amd64_get_event_nattrspfm_amd64_get_num_eventsintel_core_supportintel_x86_modspfm_intel_x86_cfgintel_x86_attr2modpfm_intel_x86_detectpfm_intel_x86_add_defaultspfm_intel_x86_get_encodingpfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_event_is_validpfm_intel_x86_validate_tablepfm_intel_x86_get_event_attr_infopfm_intel_x86_get_event_infopfm_intel_x86_valid_pebspfm_intel_x86_get_event_nattrspfm_intel_x86_can_auto_encodeintel_x86_arch_supportpfm_intel_x86_arch_terminateintel_atom_supportintel_nhm_unc_supportintel_wsm_unc_supportpfm_nhm_data_src_descintel_nhm_supportintel_nhm_ex_supportintel_wsm_sp_supportintel_wsm_dp_supportintel_snb_supportintel_snb_ep_supportintel_snb_unc_cbo0_supportintel_snb_unc_cbo1_supportintel_snb_unc_cbo2_supportintel_snb_unc_cbo3_supportintel_ivb_supportintel_ivb_ep_supportintel_ivb_unc_cbo0_supportintel_ivb_unc_cbo1_supportintel_ivb_unc_cbo2_supportintel_ivb_unc_cbo3_supportintel_hsw_supportsnbep_unc_modspfm_intel_snbep_unc_detectsnbep_unc_add_defaultspfm_intel_snbep_unc_get_encodingpfm_intel_snbep_unc_can_auto_encodepfm_intel_snbep_unc_get_event_attr_infointel_snbep_unc_cb0_supportintel_snbep_unc_cb1_supportintel_snbep_unc_cb2_supportintel_snbep_unc_cb3_supportintel_snbep_unc_cb4_supportintel_snbep_unc_cb5_supportintel_snbep_unc_cb6_supportintel_snbep_unc_cb7_supportintel_snbep_unc_ha_supportintel_snbep_unc_imc0_supportintel_snbep_unc_imc1_supportintel_snbep_unc_imc2_supportintel_snbep_unc_imc3_supportintel_snbep_unc_pcu_supportintel_snbep_unc_qpi0_supportintel_snbep_unc_qpi1_supportintel_snbep_unc_ubo_supportintel_snbep_unc_r2pcie_supportintel_snbep_unc_r3qpi0_supportintel_snbep_unc_r3qpi1_supportintel_knc_supportnetburst_modspfm_netburst_get_encodingnetburst_supportnetburst_p_supportamd64_k7_supportamd64_k8_revb_supportamd64_k8_revc_supportamd64_k8_revd_supportamd64_k8_reve_supportamd64_k8_revf_supportamd64_k8_revg_supportamd64_fam10h_barcelona_supportamd64_fam10h_shanghai_supportamd64_fam10h_istanbul_supportamd64_fam11h_turion_supportamd64_fam12h_llano_supportamd64_fam14h_bobcat_supportamd64_fam15h_interlagos_support// 904 ` pfmlib_perf_event_pmu.o/ pfmlib_perf_event.o/ pfmlib_intel_x86_perf_event.o/ pfmlib_amd64_perf_event.o/ pfmlib_intel_netburst_perf_event.o/ pfmlib_intel_snbep_unc_perf_event.o/ pfmlib_intel_core.o/ pfmlib_intel_x86.o/ pfmlib_intel_x86_arch.o/ pfmlib_intel_atom.o/ pfmlib_intel_nhm_unc.o/ pfmlib_intel_nhm.o/ pfmlib_intel_wsm.o/ pfmlib_intel_snb.o/ pfmlib_intel_snb_unc.o/ pfmlib_intel_ivb.o/ pfmlib_intel_ivb_unc.o/ pfmlib_intel_hsw.o/ pfmlib_intel_snbep_unc.o/ pfmlib_intel_snbep_unc_cbo.o/ pfmlib_intel_snbep_unc_ha.o/ pfmlib_intel_snbep_unc_imc.o/ pfmlib_intel_snbep_unc_pcu.o/ pfmlib_intel_snbep_unc_qpi.o/ pfmlib_intel_snbep_unc_ubo.o/ pfmlib_intel_snbep_unc_r2pcie.o/ pfmlib_intel_snbep_unc_r3qpi.o/ pfmlib_intel_knc.o/ pfmlib_intel_netburst.o/ pfmlib_amd64_k7.o/ pfmlib_amd64_k8.o/ pfmlib_amd64_fam10h.o/ pfmlib_amd64_fam11h.o/ pfmlib_amd64_fam12h.o/ pfmlib_amd64_fam14h.o/ pfmlib_amd64_fam15h.o/ pfmlib_common.o/1386324439 1009 1009 100664 73720 ` ELF>@@UHH}uHE@EE EE]UHHHXH`HhLpLxt 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unsigned intmax_encoding_flags2_IO_read_baseget_event_nextthis_unused2pfmlib_find_osintel_snbep_unc_r2pcie_supportPFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTintel_snbep_unc_imc3_supportPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000_ISxdigitpfm_dtype_tPFM_ATTR_UMASK_old_offsetintel_snbep_unc_cb2_supportargsretvalPFM_PMU_INTEL_IVB_EPamd64_k8_reve_supporthas_umintel_nhm_unc_supportPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64verbosePFM_PMU_I386_PMlong long intpfmlib_pmu_initializedpfmlib_attr_desc_tva_listmaxlenintel_snb_ep_support_ISupperPFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1_IScntrl_IO_write_endPFM_PMU_INTEL_PPROeinfointel_ivb_unc_cbo2_supportgp_offsetintel_snbep_unc_ubo_supportintel_snbep_unc_r3qpi1_supportnpattrscountdfl_booleventaddrpfmlib_check_event_pattrs_IO_buf_baseunsigned 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intintel_snbep_unc_cb3_supportPFM_DTYPE_CHAR8reg_save_areapattrsamd64_k8_revf_supportmaxszPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP_ISblank__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64is_present_ISalnumPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameamd64_fam11h_turion_supportis_dfl_ISspacePFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12pfmlib_common.cdebugamd64_fam10h_shanghai_supportPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3intel_snb_supportpfmlib_compact_attrs_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREpfmlib_strconcat_next__off64_tcodeintel_ivb_ep_supportpfmlib_getlintel_knc_supportdtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_Ppfmlib_err_listPFM_PMU_INTEL_HSWamd64_fam14h_bobcat_supportPFM_PMU_SPARC_ULTRA3Iosidpmu_id_ISlowerpfm_get_pmu_infoPFM_DTYPE_UINT64stderrshort intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tintel_snb_unc_cbo3_supportuargcodespfmlib_pmu_activeneventsamd64_fam10h_istanbul_supportget_event_firsthas_val/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetpfmlib_init_envPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_tintel_snbep_unc_ha_supportreserved_bits__pfm_dbprintfpfm_initializeintel_ivb_unc_cbo1_supportpfmlib_os_perfencodePFM_PMU_INTEL_SNBEP_UNC_PCUinactivedetectPFM_OS_MAX_IO_read_endintel_atom_supportpfm_event_info_tpfmlib_init_pmusintel_core_supportPFM_PMU_INTEL_X86_ARCHpfmlib_init_osPFM_PMU_AMD64_FAM10H_ISTANBUL_filenointel_snbep_unc_cb4_supportamd64_k8_revg_supportreserved_ISdigitintel_snbep_unc_r3qpi0_supportPFM_PMU_INTEL_NHM_EXshort unsigned intstdoutdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPpfmlib_pmu_validate_encodingPFM_DTYPE_FIXEDnum_cntrspfmlib_os_tpnamePFM_PMU_ITANIUM2__pfm_vbprintfPFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTpfmlib_same_attrPFM_PMU_MIPS_74Kdisplay_regpfmlib_pmusforced_pmupfm_os_tdatasupported_plmpfmlib_event_desc_tpfmlib_get_pmu_by_typepfmlib_pidx2idxpfm_get_event_nextpfmlib_parse_equiv_eventpfmlib_match_forced_pmuGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx #AC ^ <AC  \AC  |AC  AC  AC  tAC o AC  AC W <AC W \AC O |!AC \ AC  RAC M AC   AC  AC   <AC E `zAC u |AC w AC  AC  EAC @ vAC q  AC  @AC   `AC E AC  0AC k oAC j AC  1AC l $ AC F DiAC d dAC  AC  wAC r AC   UAC HH IAC D (AC  HAC  hAC  \AC W IAC D 1AC l AC   AC J .symtab.strtab.shstrtab.rela.text.rela.data.bss.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @A4@+4 &1`7p 6`7C4@3)>x>Ogibm0]00 v4mjq` 0uN0- (xH8 @u #!-8<24R1h tpt=A]y!BRm #x <J z^lF | ` G]  $o=K@h[ls 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intsel_unit_maskPFM_PMU_MAXpme_countPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1wakeup_eventsngrpsample_id_allPFM_DTYPE_MAXpfm_event_info_tsample_regs_useruequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEfilenameos_datapmu_terminateunsigned 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unsigned intmax_encodingPERF_TYPE_MAXusel_res1usel_res2usel_res3usel_res4_flags2intel_x86_eflagPERF_TYPE_RAW_IO_read_basehas_pebsget_event_nextthis_unused2near_retPFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000sample_stack_userpfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6sel_event_selectPFM_PMU_PPC970MPos_detectPERF_TYPE_SOFTWAREsvalPFM_PMU_GEN_IA64cpl_neq0PFM_PMU_I386_PMlong long intpfmlib_attr_desc_twakeup_watermarknear_ind_jmpunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endread_formatPFM_PMU_INTEL_PPROumaskssel_res2sel_ennpattrscountdfl_boolevent_IO_buf_baseunsigned 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intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesexclude_hostget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved2reserved_bitsinherit_statbp_typeenable_on_execsel_intxsel_osPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAXexclude_callchain_kernelexclude_idle_IO_read_endmodmsknear_ind_callsel_pcuint32_tPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenopfm_intel_x86_perf_validate_pattrsbranch_sample_typesample_freqreservedPFM_PMU_INTEL_NHM_EXfreqshort unsigned inthas_ldlatdfl_intusel_intvalidate_tableusel_invpmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPintel_x86_uflagPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regsel_usrnhm_lbr_selectpfm_os_tsupported_plmpfmlib_event_desc_tPERF_TYPE_HARDWAREpfm_intel_x86_reg__reserved_1__reserved_2perf_event_attrGCC: (GNU) 4.7.2 20120921 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P(pmuA@`(iCWl)CWh% $ > $ > : ; I  I&I&  : ; : ;I8 : ;  : ;  : ; I8 I!I/ 'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8! : ; "'# : ; $ : ; I 8 %.?: ; 'I@B&: ; I': ; I(4: ; I)4: ; I*4I4+.?: ; '@B,L8 /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmonpfmlib_amd64_perf_event.ctypes.hstddef.hstdint.hstdio.hlibio.hpfmlib.hpfmlib_priv.hpfmlib_amd64_priv.hperf_event.h "gZ(x0Y2w$wwwgefJ#size_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEAMD64_FAM10H_REV_BAMD64_FAM10H_REV_CAMD64_FAM10H_REV_D_IO_save_endPFM_PMU_AMD64PERF_TYPE_TRACEPOINTexclude_hv__func__PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2commconfigPFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPERF_TYPE_HW_CACHEPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1wakeup_eventssample_id_allPFM_DTYPE_MAXpfm_event_info_tsample_regs_userPFM_PMU_PPC970PFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tprecise_ipPFM_PMU_MIPS_R12000chardfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tsample_periodPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BAMD64_K8_REV_DAMD64_K8_REV_EAMD64_K8_REV_FAMD64_K8_REV_GPFM_ATTR_MOD_INTEGERattrPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_ATTR_MAXPFM_PMU_MIPS_5KC_posmmapPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markerspfmlib_amd64_perf_event.ctaskPFM_PMU_MIPS_VR5432pfm_event_attr_info_tconfig1config2dfl_val64PFM_DTYPE_RATIOinherit_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1PFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIdisabledlong unsigned intmax_encodingPERF_TYPE_MAX_flags2PERF_TYPE_RAW_IO_read_baseget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000sample_stack_userpfm_dtype_tPFM_ATTR_UMASK_old_offsetPFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectPERF_TYPE_SOFTWAREsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_twakeup_watermarkPFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSAMD64_K8_REV_BPFM_PMU_SPARC_NIAGARA1_IO_write_endread_formatPFM_PMU_INTEL_PPROnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3compact__pad1__pad2__pad3__pad4__pad5exclude_kernel_sbufis_precisepfm_amd64_get_perf_encodingPFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOsample_typewatermarkmmap_dataget_event_encoding_flagsPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOPFM_PMU_INTEL_WSM_UNCfstrAMD64_CPU_UNpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsbp_addrnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12perf_type_idPERF_TYPE_BREAKPOINTpfm_amd64_perf_validate_pattrsPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3exclude_user_IO_backup_base_shortbufexclude_guestPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREexclude_callchain_user_next__off64_tcodepinneddtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Iosidbp_lenPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tcodesexclude_hostget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsinherit_statbp_typeenable_on_execPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAXexclude_callchain_kernelexclude_idle_IO_read_endAMD64_FAM14H_REV_Buint32_tPFM_PMU_INTEL_X86_ARCHAMD64_K8_REV_CPFM_PMU_AMD64_FAM10H_ISTANBUL_filenobranch_sample_typesample_freqreservedPFM_PMU_INTEL_NHM_EXfreqshort unsigned intdfl_intvalidate_tableAMD64_K7pmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmexclusivepfmlib_event_desc_tPERF_TYPE_HARDWARE__reserved_1__reserved_2perf_event_attrGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx AC  <AC ~ .symtab.strtab.shstrtab.rela.text.data.bss.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @L4x&,1l>9X5!J@]0XXV0 q$lV }0W0,-@,@,XV0,2 P4P   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size_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEP4_EVENT_EXECUTION_EVENT_IO_save_endPFM_PMU_AMD64PERF_TYPE_TRACEPOINTexclude_hvPFM_PMU_MIPS_SB1P4_EVENT_RESPONSE_IO_write_basePFM_PMU_SPARC_NIAGARA2commconfigPFM_PMU_INTEL_PII_lockP4_EVENT_RETIRED_BRANCH_TYPEequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtypeP4_EVENT_TC_MISC_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainP4_EVENT_SCALAR_DP_UOPPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFpfm_netburst_get_perf_encodingPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEP4_EVENT_SNOOPnattrsPFM_PMU_TYPE_UNKNOWNPERF_TYPE_HW_CACHEPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1wakeup_eventssample_id_allPFM_DTYPE_MAXnetburst_entry_tpfm_event_info_tsample_regs_userPFM_PMU_PPC970P4_EVENT_UOPS_RETIREDPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEevent_selectP4_EVENT_BPU_FETCH_REQUESTos_datapmu_terminateunsigned charP4_EVENT_UOP_QUEUE_WRITESPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXpfmlib_intel_netburst_perf_event.cctrlPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tprecise_ipPFM_PMU_MIPS_R12000charP4_EVENT_BNRdfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tP4_EVENT_ITLB_REFERENCEsample_periodP4_EVENT_BSQ_CACHE_REFERENCEPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERattrPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsexclusiveP4_EVENT_IOQ_ALLOCATIONPFM_PMU_MIPS_5KCP4_EVENT_PACKED_SP_UOP_posmmapP4_EVENT_MACHINE_CLEARPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersP4_EVENT_MEMORY_CANCELPFM_ATTR_MAXtaskevent_masksPFM_PMU_MIPS_VR5432pfm_event_attr_info_tconfig1config2P4_EVENT_MISPRED_BRANCH_RETIREDP4_EVENT_RETIRED_MISPRED_BRANCH_TYPEdfl_val64P4_EVENT_REPLAY_EVENTPFM_DTYPE_RATIOinherit_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1PFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tP4_EVENT_STORE_PORT_REPLAYPFM_PMU_AMD64_FAM10H_SHANGHAIdisabledlong unsigned intP4_EVENT_INSTR_COMPLETEDmax_encodingPERF_TYPE_MAX_flags2PERF_TYPE_RAW_IO_read_baseget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000sample_stack_userpfm_dtype_tPFM_ATTR_UMASK_old_offsetPFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectPERF_TYPE_SOFTWAREsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_twakeup_watermarkPFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1P4_EVENT_SSE_INPUT_ASSIST_IO_write_endread_formatPFM_PMU_INTEL_PPROnpattrscountdfl_boolevent_IO_buf_baseunsigned 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intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLP4_EVENT_MEMORY_COMPLETEPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9P4_EVENT_WC_BUFFERperf_nameis_dflP4_EVENT_TC_DELIVER_MODEPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12perf_type_idPERF_TYPE_BREAKPOINTnetburst_eventsPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3exclude_user_IO_backup_base_shortbufexclude_guestPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREP4_EVENT_128BIT_MMX_UOPexclude_callchain_user_next__off64_tcodeP4_EVENT_PACKED_DP_UOPpinneddtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Iosidallowed_escrsbp_lenPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tcodesexclude_hostget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_tP4_EVENT_BSQ_ACTIVE_ENTRIESreserved_bitsinherit_statP4_EVENT_GLOBAL_POWER_EVENTSP4_EVENT_FRONT_END_EVENTbp_typeenable_on_execP4_EVENT_X87_FP_UOPPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAXexclude_callchain_kernelexclude_idlenetburst_event_mask_t_IO_read_enduint32_tPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenobranch_sample_typesample_freqreservedPFM_PMU_INTEL_NHM_EXfreqshort unsigned intP4_EVENT_BRANCH_RETIREDdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPP4_EVENT_UOP_TYPEPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KP4_EVENT_TC_MS_XFERPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kwatermarkdisplay_regP4_EVENT_MOB_LOAD_REPLAYpfm_os_tsupported_plmpfmlib_event_desc_tPERF_TYPE_HARDWAREP4_EVENT_INSTR_RETIREDP4_EVENT_PAGE_WALK_TYPE__reserved_1__reserved_2perf_event_attrGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx AC  <OAC J .symtab.strtab.shstrtab.rela.text.data.bss.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @ P90&L,L6L?19h%B3U0P^0id_ u0c00-1 1X0_0x1 7  8   $C]Opfmlib_intel_netburst_perf_event.cpfm_netburst_get_perf_encodingpfm_netburst_get_encodingpfm_netburst_perf_validate_pattrspfmlib_compact_pattrsW    P! ) 0 7 > E x L S a f pq   j  g A  r    & 3 @ M 7Z Zg t T t  ]  z   z   i  !  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.Y2˻v$$yvgywg_fJ(sel_unit_masksize_tsizetypefar_branchvalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEusel_event_IO_save_endPFM_PMU_AMD64exclude_hvPFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2near_rel_callcommconfigPFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainnhm_unc_fixedPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1wakeup_eventssample_id_allPFM_DTYPE_MAXpfm_event_info_tsample_regs_userPFM_PMU_PPC970PFM_PMU_INTEL_SNBEP_UNC_CB0signed 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charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlnhm_uncPFM_PMU_MIPS_R10000no_smplPFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tprecise_ipPFM_PMU_MIPS_R12000charcpl_eq0dfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pnameusel_edge_IO_lock_tsample_periodPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9Bsel_intxcpPFM_ATTR_MOD_INTEGERattrPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsexclusivePFM_PMU_MIPS_5KC_posmmapPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXtaskreserved1perfevtselPFM_PMU_MIPS_VR5432pfm_event_attr_info_tconfig1config2usel_umaskdfl_val64PFM_DTYPE_RATIOinherit_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1PFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8sel_intPFM_PMU_ARM_1176sel_invPFM_PMU_CELLpfm_pmu_type_tsel_edgePFM_PMU_AMD64_FAM10H_SHANGHAIdisabledlong unsigned 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intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_namepfm_amd64_get_num_eventsis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12tillPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREsel_event_mask_nextl1tlbmiss__off64_tcodedtypeget_event_nattrsamd64_num_modsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Iosidsel_cnt_maskPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tpfm_amd64_get_event_nextgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gpfm_amd64_get_event_attr_infoPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved2reserved_bitspfm_amd64_get_event_nattrsphyaddrvalidamd64_modssel_osPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAXl1tlbpgsz_IO_read_endmodmskAMD64_FAM14H_REV_Bsel_pcpfmlib_popcntPFM_PMU_INTEL_X86_ARCHAMD64_K8_REV_CPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedcpuidPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tableAMD64_K7pmu_revamd64_till_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KgrpcountsPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regsel_usrpfm_os_tsupported_plmpfmlib_event_desc_tmaxcntGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx 1AC l  <^AC AX `KAC F IAC D ]AC X 'AC b 'AC b AC O  'AC b @AC z `BAC }  AC E  AC E uAC p AC   AC E $,AC K TsAC n tAC   T AC HG NAC I AC { CAC ~ 6AC 1  8AC E \ AC  |<AC w RAC M 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" * @1d#$D dUi 0Xx  8<1`M&8'/177 1386324439 1009 1009 100664 77936 ` ELF>й@@UHSH(H}E}tEFt4wHHӉHH% HuH([]UHH}]  PORT_0On port 0PORT_1On port 1PORT_2On port 2PORT_3On port 3PORT_4On port 4PORT_5On port 5ANYOn any portPORT_0:PORT_1:PORT_2:PORT_3:PORT_4:PORT_5 ? STALoads blocked by a preceding store with unknown addressSTDLoads blocked by a preceding store with unknown dataOVERLAP_STORELoads that partially overlap an earlier store, or 4K equived with a previous storeUNTIL_RETIRELoads blocked until retirementL1DLoads blocked by the L1 data cache ORDERCycles while store is waiting for a preceding store to be globally observedSNOOPA store is blocked due to a conflict with an external or internal snoopNTAStreaming SIMD Extensions (SSE) Prefetch NTA instructions executedL1Streaming SIMD Extensions (SSE) PrefetchT0 instructions executedL2Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executedSTORESStreaming SIMD Extensions (SSE) Weakly-ordered store instructions executedAny memory access that missed the DTLBMISS_LDDTLB misses due to load operationsL0_MISS_LDL0 DTLB misses due to load operationsMISS_STDTLB misses due to store operationsRESETMemory disambiguation reset cyclesSUCCESSNumber of loads that were successfully disambiguatedCOUNTNumber of page-walks executedCYCLESDuration of page-walks in core cyclesFPDelayed bypass to FP operationSIMDDelayed bypass to SIMD operationLOADDelayed bypass to load operationSELFThis coreBOTH_CORESBoth cores@ All inclusivePREFETCHHardware prefetch onlyEXCL_PREFETCHExclude hardware prefetch@ 0 MESIAny cacheline accessM_STATE:E_STATE:S_STATE:I_STATEI_STATEInvalid cachelineS_STATEShared cachelineE_STATEExclusive cachelineM_STATEModified cacheline@  @ 0  CORE_PCore cycles when core is not haltedBUSBus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratioNO_OTHERBus cycles when core is active and the other is halted  LOADSCache line split loads from the L1 data cacheCache line split stores to the L1 data cacheStreaming SIMD Extensions (SSE) Prefetch NTA instructions missing all cache levelsStreaming SIMD Extensions (SSE) PrefetchT0 instructions missing all cache levelsStreaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions missing all cache levelsREQUESTSL1 data cache prefetch requestsTHIS_AGENTThis agentALL_AGENTSAny agent on the bus@    Any external snoop responseCLEANExternal snoop CLEAN responseHITExternal snoop HIT responseHITMExternal snoop HITM response   L1 data cache is snooped by other coreSHAREL1 data cache is snooped for sharing by other coreINVALIDATEL1 data cache is snooped for Invalidation by other core @ SMALL_MISSITLB small page missesLARGE_MISSITLB large page missesFLUSHITLB flushesMISSESITLB misses@FULLCycles during which the instruction queue is fullDECODEDInstructions decodedCISC_DECODEDCISC instructions decodedSYNCHESP register content synchronizationADDITIONSESP register automatic additionsMULSIMD packed multiply micro-ops executedSHIFTSIMD packed shift micro-ops executedPACKSIMD pack micro-ops executedUNPACKSIMD unpack micro-ops executedLOGICALSIMD packed logical micro-ops executedARITHMETICSIMD packed arithmetic micro-ops executed ANY_PInstructions retired (Precise Event)Instructions retired, which contain a loadInstructions retired, which contain a storeOTHERInstructions retired, with no load or store operation FXCHFXCH instructions retiredRetired floating-point computational operations (Precise Event) LD_IND_BRFused load+op or load+indirect branch retiredSTD_STAFused store address + data retiredMACRO_FUSIONRetired instruction pairs fused into one micro-opNON_FUSEDNon-fused micro-ops retiredFUSEDFused micro-ops retiredMicro-ops retired SMCSelf-Modifying Code detectedMEM_ORDERExecution pipeline restart due to memory ordering conflict or memory disambiguation mispredictionRetired branch instructionsPRED_NOT_TAKENRetired branch instructions that were predicted not-takenMISPRED_NOT_TAKENRetired branch instructions that were mispredicted not-takenPRED_TAKENRetired branch instructions that were predicted takenMISPRED_TAKENRetired branch instructions that were mispredicted takenTAKENRetired taken branch instructions  PACKED_SINGLERetired Streaming SIMD Extensions (SSE) packed-single instructionsSCALAR_SINGLERetired Streaming SIMD Extensions (SSE) scalar-single instructionsPACKED_DOUBLERetired Streaming SIMD Extensions 2 (SSE2) packed-double instructionsSCALAR_DOUBLERetired Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsVECTORRetired Streaming SIMD Extensions 2 (SSE2) vector integer instructionsRetired Streaming SIMD instructions (Precise Event) Retired computational Streaming SIMD Extensions (SSE) packed-single instructionsRetired computational Streaming SIMD Extensions (SSE) scalar-single instructionsRetired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructionsRetired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsL1D_MISSRetired loads that miss the L1 data cache (Precise Event)L1D_LINE_MISSL1 data cache line missed by retired loads (Precise Event)L2_MISSRetired loads that miss the L2 cache (Precise Event)L2_LINE_MISSL2 cache line missed by retired loads (Precise Event)DTLB_MISSRetired loads that miss the DTLB (Precise Event)TO_FPTransitions from MMX (TM) Instructions to Floating Point InstructionsTO_MMXTransitions from Floating Point to MMX (TM) InstructionsROB_READ_PORTROB read port stalls cyclesPARTIAL_CYCLESPartial register stall cyclesFLAGSFlag stall cyclesFPSWFPU status word stallAll RAT stall cycles ESSegment rename stalls - ES DSSegment rename stalls - DSFSSegment rename stalls - FSGSSegment rename stalls - GSAny (ES/DS/FS/GS) segment rename stall Segment renames - ESSegment renames - DSSegment renames - FSSegment renames - GSAny (ES/DS/FS/GS) segment rename ROB_FULLCycles during which the ROB is fullRS_FULLCycles during which the RS is fullLD_STCycles during which the pipeline has exceeded load or store limit or waiting to commit all storesFPCWCycles stalled due to FPU control word writeBR_MISS_CLEARCycles stalled due to branch mispredictionResource related stalls UNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)INSTRUCTION_RETIREDCount the number of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias from INSTRUCTION_RETIREDUNHALTED_REFERENCE_CYCLESUnhalted reference cyclesLLC_REFERENCESCount each request originating equiv the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESILAST_LEVEL_CACHE_REFERENCESThis is an alias for LLC_REFERENCESLLC_MISSESCount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATELAST_LEVEL_CACHE_MISSESThis is an alias for LLC_MISSESBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.BR_INST_RETIRED:ANYMISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware.BR_INST_RETIRED_MISPREDRS_UOPS_DISPATCHED_CYCLESCycles micro-ops dispatched for executionRS_UOPS_DISPATCHEDNumber of micro-ops dispatched for executionRS_UOPS_DISPATCHED_NONENumber of of cycles in which no micro-ops is dispatched for executionRS_UOPS_DISPATCHED:i=1:c=1LOAD_BLOCKLoads blockedSB_DRAIN_CYCLESCycles while stores are blocked due to store buffer drainSTORE_BLOCKCycles while store is waitingSEGMENT_REG_LOADSNumber of segment register loadsSSE_PRE_EXECStreaming SIMD Extensions (SSE) Prefetch instructions executedDTLB_MISSESMemory accesses that missed the DTLBMEMORY_DISAMBIGUATIONMemory disambiguationPAGE_WALKSFP_COMP_OPS_EXEFloating point computational micro-ops executedFP_ASSISTFloating point assistsMultiply operations executedDIVDivide operations executedCYCLES_DIV_BUSYCycles the divider is busyIDLE_DURING_DIVCycles the divider is busy and all other execution units are idleDELAYED_BYPASSDelayed bypassL2_ADSCycles L2 address bus is in useL2_DBUS_BUSY_RDCycles the L2 transfers data to the coreL2_LINES_INL2 cache missesL2_M_LINES_INL2 cache line modificationsL2_LINES_OUTL2 cache lines evictedL2_M_LINES_OUTModified lines evicted from the L2 cacheL2_IFETCHL2 cacheable instruction fetch requestsL2_LDL2 cache readsL2_STL2 store requestsL2_LOCKL2 locked accessesL2_RQSTSL2 cache requestsL2_REJECT_BUSQRejected L2 cache requestsL2_NO_REQCycles no L2 cache requests are pendingEIST_TRANSNumber of Enhanced Intel SpeedStep(R) Technology (EIST) transitionsTHERMAL_TRIPNumber of thermal tripsCPU_CLK_UNHALTEDL1D_CACHE_LDL1 cacheable data readsL1D_CACHE_STL1 cacheable data writesL1D_CACHE_LOCKL1 data cacheable locked readsL1D_ALL_REFAll references to the L1 data cacheL1D_ALL_CACHE_REFL1 Data cacheable reads and writesL1D_REPLCache lines allocated in the L1 data cacheL1D_M_REPLModified cache lines allocated in the L1 data cacheL1D_M_EVICTModified cache lines evicted from the L1 data cacheL1D_PEND_MISSTotal number of outstanding L1 data cache misses at any cycleL1D_SPLITCache line split from L1 data cacheSSE_PRE_MISSStreaming SIMD Extensions (SSE) instructions missing all cache levelsLOAD_HIT_PRELoad operations conflicting with a software prefetch to the same addressL1D_PREFETCHL1 data cache prefetchBUS_REQUEST_OUTSTANDINGNumber of pending full cache line read transactions on the bus occurring in each cycleBUS_BNR_DRVNumber of Bus Not Ready signals assertedBUS_DRDY_CLOCKSBus cycles when data is sent on the busBUS_LOCK_CLOCKSBus cycles when a LOCK signal is assertedBUS_DATA_RCVBus cycles while processor receives dataBUS_TRANS_BRDBurst read bus transactionsBUS_TRANS_RFORFO bus transactionsBUS_TRANS_WBExplicit writeback bus transactionsBUS_TRANS_IFETCHInstruction-fetch bus transactionsBUS_TRANS_INVALInvalidate bus transactionsBUS_TRANS_PWRPartial write bus transactionBUS_TRANS_PPartial bus transactionsBUS_TRANS_IOIO bus transactionsBUS_TRANS_DEFDeferred bus transactionsBUS_TRANS_BURSTBurst (full cache-line) bus transactionsBUS_TRANS_MEMMemory bus transactionsBUS_TRANS_ANYAll bus transactionsEXT_SNOOPExternal snoops responsesCMP_SNOOPBUS_HIT_DRVHIT signal assertedBUS_HITM_DRVHITM signal assertedBUSQ_EMPTYBus queue is emptySNOOP_STALL_DRVBus stalled for snoopsBUS_IO_WAITIO requests waiting in the bus queueL1I_READSInstruction fetchesL1I_MISSESInstruction Fetch Unit missesITLBINST_QUEUECYCLES_L1I_MEM_STALLEDCycles during which instruction fetches are stalledILD_STALLInstruction Length Decoder stall cycles due to a length changing prefixBR_INST_EXECBranch instructions executedBR_MISSP_EXECMispredicted branch instructions executedBR_BAC_MISSP_EXECBranch instructions mispredicted at decodingBR_CND_EXECConditional branch instructions executedBR_CND_MISSP_EXECMispredicted conditional branch instructions executedBR_IND_EXECIndirect branch instructions executedBR_IND_MISSP_EXECMispredicted indirect branch instructions executedBR_RET_EXECRET instructions executedBR_RET_MISSP_EXECMispredicted RET instructions executedBR_RET_BAC_MISSP_EXECRET instructions executed mispredicted at decodingBR_CALL_EXECCALL instructions executedBR_CALL_MISSP_EXECMispredicted CALL instructions executedBR_IND_CALL_EXECIndirect CALL instructions executedBR_TKN_BUBBLE_1Branch predicted taken with bubble IBR_TKN_BUBBLE_2Branch predicted taken with bubble IIMACRO_INSTSESPSIMD_UOPS_EXECSIMD micro-ops executed (excluding stores)SIMD_SAT_UOP_EXECSIMD saturated arithmetic micro-ops executedSIMD_UOP_TYPE_EXECINST_RETIREDInstructions retiredX87_OPS_RETIREDUOPS_RETIREDMACHINE_NUKESBR_INST_RETIREDRetired mispredicted branch instructions (Precise_Event)CYCLES_INT_MASKEDCycles during which interrupts are disabledCYCLES_INT_PENDING_AND_MASKEDCycles during which interrupts are pending and disabledSIMD_INST_RETIREDHW_INT_RCVHardware interrupts receivedITLB_MISS_RETIREDRetired instructions that missed the ITLBSIMD_COMP_INST_RETIREDMEM_LOAD_RETIREDRetired loads that miss the L1 data cacheFP_MMX_TRANSSIMD_ASSISTSIMD assists invokedSIMD_INSTR_RETIREDSIMD Instructions retiredSIMD_SAT_INSTR_RETIREDSaturated arithmetic instructions retiredRAT_STALLSSEG_RENAME_STALLSSEG_REG_RENAMESRESOURCE_STALLSBR_INST_DECODEDBranch instructions decodedBOGUS_BRBogus branchesBACLEARSBACLEARS assertedPREF_RQSTS_UPUpward prefetches issued from the DPLPREF_RQSTS_DNDownward prefetches issued from the DPL<.O.O.A.A  !#$%&'() *+. 0 2:;<@ABCCEFGHIKLN`abcdefghijklmnopwxz{}~Intel Corecoreint^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW 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intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kcore_l2_ifetchcore_memory_disambiguation_IO_markercore_dtlb_missesPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tcore_delayed_bypasscore_sse_pre_missuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEcore_uops_retiredos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlcore_l2_ldPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tpfmlib_intel_core.cPFM_PMU_MIPS_R12000charmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tcore_br_inst_retiredPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERcore_rat_stallsPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqcore_l2_adsdfl_val64modhwcore_inst_retiredPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIpfm_core_inituflagslong unsigned intmax_encoding_flags2core_seg_reg_renames_IO_read_basepfm_core_detectcore_bus_request_outstandingget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000core_l2_lines_inpfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endPFM_PMU_INTEL_PPROcore_l1d_cache_ldumasksnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOcore_simd_comp_inst_retiredget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CFcore_page_walks_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMcore_rs_uops_dispatched_cyclessteppingcan_auto_encodeget_event_attr_infosizeintel_x86_modslong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64core_sse_pre_execPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_namecore_macro_instsis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3core_mem_load_retired_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREcore_simd_inst_retired_next__off64_tcodecore_l1d_splitdtypecore_resource_stallsget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKcore_simd_uop_type_execPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodescore_cpu_clk_unhaltedget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_tintel_core_pecore_x87_ops_retiredreserved_bitscore_itlbarch_versioncore_machine_nukesPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endcore_ext_snooppfm_intel_x86_config_tmodmskintel_core_supportPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPcore_cmp_snoopPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx  mAC Ec  @AC T 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regionintxcpdo not count occurrences inside aborted transactional memory region[0x%lx event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d any=%d] [0x%lx] %s GenuineIntelpfmlib_intel_x86.c%s (%s.%d): added default %s for group %d j=%d idx=%d %s (%s.%d): two max_grpid, old=%d new=%d %s (%s.%d): no default found for event %s unit mask group %d (max_grpid=%d) %s (%s.%d): max_grpid=%d nattrs=%d k=%d %s (%s.%d): check: max_grpid=%d %s (%s.%d): exclusive unit mask group error %s (%s.%d): umask %s does not support unit mask combination within group %d %s (%s.%d): cannot override event with two different codes for %s %s (%s.%d): raw umask is 8-bit wide %s (%s.%d): event %s: umask from grp > %d %s (%s.%d): required modifiers missing: 0x%x %s:%s:0x%x%s (%s.%d): passed ldlat= but not using ldlat umask %s (%s.%d): missing ldlat= for umask, forcing to default %d cycles %s (%s.%d): edge requires cmask >= 1 :%s=%lu:%s=%dpmu: %s missing attr_desc pmu: %s supported_plm not set ??pmu: %s event%d: :: no name (prev event was %s) pmu: %s event%d: %s :: no description pmu: %s event%d: %s :: cntmsk=0 pmu: %s event%d: %s :: ngrp cannot be zero pmu: %s event%d: %s :: numasks but no umasks pmu: %s event%d: %s :: numasks=0 but umasks defined pmu: %s event%d: %s :: ngrp must be zero pmu: %s event%d: %s :: ngrp too big (max=%d) pmu: %s events %s and %s have the same code 0x%x pmu: %s event%d: %s umask%d :: no name pmu: %s event%d: %s umask%d: %s :: modhw not subset of modmsk pmu: %s event%d: umask%d: %s :: no description pmu: %s event%d: %s umask%d: %s :: invalid grpid %d (must be < %d) pmu: %s event%d: %s, pebs umasks but event pebs flag not set pmu: %s event%d: %s, pebs event flag but not umask has pebs flag pmu: %s event%d: %s, only one umask but no default pmu: %s event%d: %s grpid %d has 2 default umasks pmu: %s event%d: %s :: NCOMBO is unit mask only flag pmu: %s event%d: %s :: umask %s and %s have overlapping code bits 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The event count may include speculation, but excludes cache line fills due to hardware prefetchBRANCH_INSTRUCTIONS_RETIREDcount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionMISPREDICTED_BRANCH_RETIREDcount mispredicted branch instructions at retirement. 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"Ku/2cntmskinitdonepfm_intel_x86_cfgufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64__func__PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intpfm_intel_x86_arch_initPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kintel_x86_mods_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapfm_cfgpmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlnum_cntPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tintel_x86_arch_supportPFM_PMU_MIPS_R12000charmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posintel_x86_pmu_eax_tPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encodingebx_length_flags2_IO_read_baseget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64verbosePFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endmaskPFM_PMU_INTEL_PPROumasksnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisepfm_intel_x86_arch_detectPFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqpfmlib_config_tPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilycnt_widthPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMsteppingcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12debugPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3versionpfm_intel_x86_arch_terminate_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREnum_events_next__off64_tcodedtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_firstintel_x86_pmu_edx_t/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsarch_versionintel_x86_arch_pePFM_PMU_INTEL_SNBEP_UNC_PCUinactivePFM_OS_MAXx86_arch_pe_IO_read_endpfm_intel_x86_config_tmodmskcreate_arch_event_tablePFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedcpuidPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_revcheck_arch_pmu_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regforced_pmupfm_os_tpfmlib_intel_x86_arch.csupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx BAC } <\AC W \AC ~ |.AC i AC  )AC d .symtab.strtab.shstrtab.rela.text.rela.data.bss.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @xC+` &@E1 6 C( J>(Hx!Or}b 0]i0 v!qi 0#,0,6-Y6`6i87p= 0AE+7B=B\Ucr!.O   )"1Ol"pfmlib_intel_x86_arch.cintel_x86_arch_pex86_arch_pecpuidcreate_arch_event_table__func__.4354check_arch_pmupfm_intel_x86_arch_detectpfm_intel_x86_arch_init__pfm_dbprintfintel_x86_arch_supportcallocpfm_intel_x86_detectpfm_intel_x86_cfgpfm_cfgpfm_intel_x86_arch_terminatefreeintel_x86_modspfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_get_event_attr_infopfm_intel_x86_get_encodingpfm_intel_x86_get_perf_encodingpfm_intel_x86_perf_validate_pattrsi n |s }< .B^ (,$(@wH?`4H@H]!O (0 8!@"H#X$`%h&p&''    7!) 0 7  >  E WL S a Mf  q ~ 2 _ +   P  >  g    L# , 0 v = &J  W 9d fq ~    #   a I  S        '  4 w A O V b n  z <  Y z     ~  s J    y     # ? ) / U 5  ; A [G M qS Y _ e +k q w K}                4     Z              % J+ 1 7 = C I O rU 2[ b A i W p Uw p~    Z   t  3          S    + G c   e   & +- 34 P;  B  I [P zW ^ a e l 5 s z    2 L  n *       0  # K      f  "  ( .  4 : o@ 4F  L rS  f : l r x  }     P      o    8 R _ s  w     $ , g     o #  0 = W q   o     u   j p & Y 2 > J a V %b  o  |     o  m z i  5  *   ( ? K W  c o {     q  + ; k &  H      G  Q  , 8 D P / \ "h Pt D  . E   o    K  ( 4 m@ R X k z    v A     # d      h - t8 >FB B :     8 =BJ!Y    !O   VO+     [  4$ :  Y @B`!O/243 1386324440 1009 1009 100664 59248 ` ELF>`@@UHH H}E}tEHt66wHHH`H!HuUHH}]Q MESIAny cacheline accessI_STATEInvalid cachelineS_STATEShared cachelineE_STATEExclusive cachelineM_STATEModified cachelineSELFThis coreBOTH_CORESBoth coresANYAll inclusivePREFETCHHardware prefetch only @ 0 ACCESSESInstruction fetches, including uncacheacble fetchesMISSESCount all instructions fetches that miss tha icache or produce memory requests. This includes uncacheache fetches. Any instruction fetch miss is counted only once and not once for every cycle it is outstanding @ Micro-ops retiredSTALLED_CYCLESCycles no micro-ops retiredSTALLSPeriods no micro-ops retired @ 0 PACKED_SINGLERetired computational Streaming SIMD Extensions (SSE) packed-single instructionsSCALAR_SINGLERetired computational Streaming SIMD Extensions (SSE) scalar-single instructionsPACKED_DOUBLERetired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructionsSCALAR_DOUBLERetired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsSSIMD saturated arithmetic micro-ops executedARSIMD saturated arithmetic micro-ops retiredANY_PInstructions retired using generic counter (precise event) LDL1 Cacheable Data ReadsSTL1 Cacheable Data Writes!"Multiply operations executedMultiply operations retiredDivide operations executedDivide operations retiredTHIS_AGENTThis agentALL_AGENTSAny agent on the bus @ @ FLUSHITLB flushesITLB missesMUL_SSIMD packed multiply micro-ops executedMUL_ARSIMD packed multiply micro-ops retiredSHIFT_SSIMD packed shift micro-ops executedSHIFT_ARSIMD packed shift micro-ops retiredPACK_SSIMD packed micro-ops executedPACK_ARSIMD packed micro-ops retiredUNPACK_SSIMD unpacked micro-ops executedUNPACK_ARSIMD unpacked micro-ops retiredLOGICAL_SSIMD packed logical micro-ops executedLOGICAL_ARSIMD packed logical micro-ops retiredARITHMETIC_SSIMD packed arithmetic micro-ops executedARITHMETIC_ARSIMD packed arithmetic micro-ops retired Retired Streaming SIMD Extensions (SSE) packed-single instructionsRetired Streaming SIMD Extensions (SSE) scalar-single instructionsRetired Streaming SIMD Extensions 2 (SSE2) packed-double instructionsRetired Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsVECTORRetired Streaming SIMD Extensions 2 (SSE2) vector instructionsRetired Streaming SIMD instructions PREFETCHT0Streaming SIMD Extensions (SSE) PrefetchT0 instructions executedSW_L2Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executedPREFETCHNTAStreaming SIMD Extensions (SSE) Prefetch NTA instructions executed@ 0  Number of SIMD saturated arithmetic micro-ops executedNumber of SIMD saturated arithmetic micro-ops retiredSMCSelf-Modifying Code detectedRetired branch instructionsPRED_NOT_TAKENRetired branch instructions that were predicted not-takenMISPRED_NOT_TAKENRetired branch instructions that were mispredicted not-takenPRED_TAKENRetired branch instructions that were predicted takenMISPRED_TAKENRetired branch instructions that were mispredicted takenMISPREDRetired mispredicted branch instructionsTAKENRetired taken branch instructionsANY1   NON_CISC_DECODEDNon-CISC macro instructions decoded ALL_DECODEDAll Instructions decoded Number of segment register loadsBACLEARS assertedCYCLES_INT_MASKEDCycles during which interrupts are disabledCYCLES_INT_PENDING_AND_MASKEDCycles during which interrupts are pending and disabledFloating point assists for executed instructionsFloating point assists for retired instructionsDTLB_MISSMemory accesses that missed the DTLBDTLB_MISS_LDDTLB misses due to load operationsL0_DTLB_MISS_LDL0 (micro-TLB) misses due to load operationsDTLB_MISS_STDTLB misses due to store operations GOODGood store forwardsCORE_PCore cycles when core is not haltedBUSBus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratioNO_OTHERBus cycles when core is active and other is halted L2_HITRetired loads that hit the L2 cache (precise event)L2_MISSRetired loads that miss the L2 cache (precise event)Retired loads that miss the DTLB (precise event)ANY_SFloating point computational micro-ops executedANY_ARFloating point computational micro-ops retiredWALKSNumber of page-walks executedCYCLESDuration of page-walks in core cyclesUNHALTED_CORE_CYCLESUnhalted core cyclesUNHALTED_REFERENCE_CYCLESUnhalted reference cycleINSTRUCTION_RETIREDInstructions retiredINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDLLC_REFERENCESLast level of cache referencesLAST_LEVEL_CACHE_REFERENCESThis is an alias for LLC_REFERENCESLLC_MISSESLast level of cache missesLAST_LEVEL_CACHE_MISSESThis is an alias for LLC_MISSESBRANCH_INSTRUCTIONS_RETIREDBranch instructions retiredBR_INST_RETIRED:ANYMISPREDICTED_BRANCH_RETIREDMispredicted branch instruction retiredSIMD_INSTR_RETIREDSIMD Instructions retiredL2_REJECT_BUSQRejected L2 cache requestsSIMD_SAT_INSTR_RETIREDSaturated arithmetic instructions retiredICACHEInstruction fetchesL2_LOCKL2 locked accessesUOPS_RETIREDL2_M_LINES_OUTModified lines evicted from the L2 cacheSIMD_COMP_INST_RETIREDRetired computational Streaming SIMD Extensions (SSE) instructionsSNOOP_STALL_DRVBus stalled for snoopsBUS_TRANS_BURSTBurst (full cache-line) bus transactionsSIMD_SAT_UOP_EXECBUS_TRANS_IOIO bus transactionsBUS_TRANS_RFORFO bus transactionsSIMD_ASSISTSIMD assists invokedINST_RETIREDL1D_CACHEMULDIVBUS_TRANS_PPartial bus transactionsBUS_IO_WAITIO requests waiting in the bus queueL2_M_LINES_INL2 cache line modificationsL2_LINES_INL2 cache missesBUSQ_EMPTYBus queue is emptyL2_IFETCHL2 cacheable instruction fetch requestsBUS_HITM_DRVHITM signal assertedITLBITLB hitsBUS_TRANS_MEMMemory bus transactionsBUS_TRANS_PWRPartial write bus transactionBR_INST_DECODEDBranch instructions decodedBUS_TRANS_INVALInvalidate bus transactionsSIMD_UOP_TYPE_EXECSIMD micro-ops executedSIMD_INST_RETIREDRetired Streaming SIMD Extensions (SSE) instructionsCYCLES_DIV_BUSYCycles the divider is busyL2_RQSTSL2 cache requestsSIMD_UOPS_EXECSIMD micro-ops executed (excluding stores)HW_INT_RCVHardware interrupts received (warning overcounts by 2x)BUS_TRANS_BRDBurst read bus transactionsBOGUS_BRBogus branchesBUS_DATA_RCVBus cycles while processor receives dataMACHINE_CLEARSBR_INST_RETIREDL2_ADSCycles L2 address bus is in useEIST_TRANSNumber of Enhanced Intel SpeedStep(R) Technology (EIST) transitionsBUS_TRANS_WBExplicit writeback bus transactionsMACRO_INSTSMacro-instructions decodedL2_LINES_OUTL2 cache lines evicted. L2_LDL2 cache readsSEGMENT_REG_LOADSL2_NO_REQCycles no L2 cache requests are pendingTHERMAL_TRIPNumber of thermal tripsEXT_SNOOPExternal snoopsBACLEARSBranch address calculatorFP_ASSISTFloating point assistsL2_STL2 store requestsBUS_TRANS_DEFDeferred bus transactionsDATA_TLB_MISSESBUS_BNR_DRVNumber of Bus Not Ready signals assertedSTORE_FORWARDSAll store forwardsCPU_CLK_UNHALTEDBUS_TRANS_ANYAll bus transactionsMEM_LOAD_RETIREDRetired loadsX87_COMP_OPS_EXEPAGE_WALKSBUS_LOCK_CLOCKSBus cycles when a LOCK signal is assertedBUS_REQUEST_OUTSTANDINGOutstanding cacheable data read bus requests durationBUS_TRANS_IFETCHInstruction-fetch bus transactionsBUS_HIT_DRVHIT signal assertedBUS_DRDY_CLOCKSBus cycles when data is sent on the busL2_DBUS_BUSYCycles the L2 cache data bus is busy<?#??.O?.O?.A?.A????0 ???+??'??~?n??l?f???@???k??%?$?}?(?{??o?j??i? ????. ???e??d???!?:?g??&?) ??2?;?w????*?m??a??<?p??? ?c?`?h?z?b?"?Intel Atomatomint^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;H Y { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  @ W W W W  #)W$)X%ret+Wl&DW$Dh Y  {'   Y  {' Q  Y  {' ]2   Y G {' \ 7 Y q {'  a'  a' ú  Y  {'  '  '  ' 2 ' L a( g ( % ( 2  Y  { ( =  Y  {( | (  7( ) ( D ( _  Y t {(  d(  ( # ( + ( 3 ( @ ( M, a( cG ( kb 7( }} 7(  (    {P(  )J * @ +* % $ > $ > : ; I  I : ; : ;I8 : ;  : ;  : ; I8 I !I/ &I'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8  : ; !&"'#.: ; 'I@B$: ; I%4: ; I&.: ; 'I@B'4: ; I(4: ;I)4: ; I?*4: ; I?<+!,mD /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_intel_atom.ctypes.hstddef.hstdint.hstdio.hlibio.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hintel_atom_events.h )g\v)r$Y2Ycntmskpfm_intel_x86_cfgufilterssize_tsizetypepfm_intel_atom_detectvalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEatom_br_inst_retiredpfmlib_intel_atom.c_IO_save_endPFM_PMU_AMD64atom_data_tlb_missesatom_fp_assistPFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KCatom_mem_load_retired_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kintel_x86_mods_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_dataatom_bus_io_waitpmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlPFM_PMU_MIPS_R10000atom_bus_trans_pPFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000charmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KCatom_l2_reject_busq_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersatom_itlbPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqatom_uops_retireddfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encodingatom_baclears_flags2atom_l2_m_lines_out_IO_read_baseget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endatom_x87_comp_ops_exeatom_simd_sat_uop_execatom_inst_retiredPFM_PMU_INTEL_PPROumasksatom_simd_uop_type_execatom_l1d_cachenpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3atom_cpu_clk_unhalted__pad1__pad2__pad3__pad4__pad5atom_l2_lock_sbufatom_divis_preciseatom_macro_instsPFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqintel_atom_pePFM_PMU_S390X_CPUM_CFatom_simd_comp_inst_retired_modepfm_attr_ctrl_tPFM_PMU_COREDUOatom_mulatom_store_forwardsfamilyPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREatom_prefetchPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMatom_simd_inst_retiredsteppingcan_auto_encodeatom_page_walksget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64atom_icachePFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_namepfm_intel_atom_initis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeatom_cycles_int_maskedget_event_nattrsatom_bus_hitm_drvPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64atom_simd_uops_execshort intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesatom_l2_rqstsget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsarch_versionatom_machine_clearsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endintel_atom_supportpfm_intel_x86_config_tmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedatom_segment_reg_loadsPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx iAC d <AC T .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @@`+ &1;W 6Px*HYC0$Tl6go0b0 {5oqv( 0po0-BHX@0 2  )50B T @h @ P`@ @@ $;I W $k%P'**P`+P`,- /@0P 2/3E@5[@6kC@yii    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HEE@EEEHUH0H(H0@EH0H UHcHHЋ@0H0H UHcHHЋ@(H0H UHcHHЋ@,EEt{ tcLEȋEHcHHHHHHH0H(AHEȋEHcHHHHHHH0H(AHEȋEHcHHHHHHH0H(AHVEȋEHcHHHHHHH0H(AHEH0@;EH0@ HHHHEHLEDEDEEEEDEEHELT$ DL$DD$|$4$AEHƿH[]*64CH0DRAM Channel 0 open comamnds issued for read or writeCH1DRAM Channel 1 open comamnds issued for read or writeCH2DRAM Channel 2 open comamnds issued for read or writeDRAM Channel 0 page closeDRAM Channel 1 page closeDRAM Channel 2 page closeDRAM Channel 0 page missDRAM Channel 1 page missDRAM Channel 2 page missDRAM Channel 0 precharge all commandsDRAM Channel 1 precharge all commandsDRAM Channel 2 precharge all commandsDRAM Channel 0 read CAS commandsAUTOPRE_CH0DRAM Channel 0 read CAS auto page close commandsDRAM Channel 1 read CAS commandsAUTOPRE_CH1DRAM Channel 1 read CAS auto page close commandsDRAM Channel 2 read CAS commandsAUTOPRE_CH2DRAM Channel 2 read CAS auto page close commands DRAM Channel 0 refresh commandsDRAM Channel 1 refresh commandsDRAM Channel 2 refresh commandsDRAM Channel 0 write CAS commandsDRAM Channel 0 write CAS auto page close commandsDRAM Channel 1 write CAS commandsDRAM Channel 1 write CAS auto page close commandsDRAM Channel 2 write CAS commandsDRAM Channel 2 write CAS auto page close commands READ_TRACKERGQ read tracker requestsRT_LLC_MISSGQ read tracker LLC missesRT_TO_LLC_RESPGQ read tracker LLC requestsRT_TO_RTID_ACQUIREDGQ read tracker LLC miss to RTID acquiredWT_TO_RTID_ACQUIREDGQ write tracker LLC miss to RTID acquiredWRITE_TRACKERGQ write tracker LLC missesPEER_PROBE_TRACKERGQ peer probe tracker requests @Cycles GQ read tracker is full.Cycles GQ write tracker is full.Cycles GQ peer probe tracker is full.Cycles GQ read tracker is busyCycles GQ write tracker is busyCycles GQ peer probe tracker is busyQPICycles GQ data is imported from Quickpath interfaceQMCCycles GQ data is imported from Quickpath memory interfaceLLCCycles GQ data is imported from LLCCORES_02Cycles GQ data is imported from Cores 0 and 2CORES_13Cycles GQ data is imported from Cores 1 and 3QPI_QMCCycles GQ data sent to the QPI or QMCCycles GQ data sent to LLCCORESCycles GQ data sent to coresREADNumber of LLC read hitsWRITENumber of LLC write hitsPROBENumber of LLC peer probe hitsANYNumber of LLC hits M_STATELLC lines allocated in M stateE_STATELLC lines allocated in E stateS_STATELLC lines allocated in S stateF_STATELLC lines allocated in F stateLLC lines allocated LLC lines victimized in M stateLLC lines victimized in E stateLLC lines victimized in S stateI_STATELLC lines victimized in I stateLLC lines victimized in F stateLLC lines victimized Number of LLC read missesNumber of LLC write missesNumber of LLC peer probe missesNumber of LLC misses 2WAYQHL 2 way address conflicts3WAYQHL 3 way address conflictsIOHQHL IOH Tracker conflict cyclesREMOTEQHL Remote Tracker conflict cyclesLOCALQHL Local Tracker conflict cyclesCycles QHL Remote Tracker is fullCycles QHL Local Tracker is fullCycles QHL IOH Tracker is fullCycles QHL IOH is busyCycles QHL Remote Tracker is busyCycles QHL Local Tracker is busyQHL FrcAckCnflts sent to local homeCycles QHL IOH Tracker Allocate to Deallocate Read OccupancyCycles QHL Remote Tracker Allocate to Deallocate Read OccupancyCycles QHL Local Tracker Allocate to Deallocate Read OccupancyLOCAL_READSQuickpath Home Logic local read requestsLOCAL_WRITESQuickpath Home Logic local write requestsREMOTE_READSQuickpath Home Logic remote read requestsIOH_READSQuickpath Home Logic IOH read requestsIOH_WRITESQuickpath Home Logic IOH write requestsREMOTE_WRITESQuickpath Home Logic remote write requests READ_CH0Cycles QMC channel 0 busy with a read requestREAD_CH1Cycles QMC channel 1 busy with a read requestREAD_CH2Cycles QMC channel 2 busy with a read requestWRITE_CH0Cycles QMC channel 0 busy with a write requestWRITE_CH1Cycles QMC channel 1 busy with a write requestWRITE_CH2Cycles QMC channel 2 busy with a write request QMC channel 0 cancelsQMC channel 1 cancelsQMC channel 2 cancelsQMC cancels QMC channel 0 critical priority read requestsQMC channel 1 critical priority read requestsQMC channel 2 critical priority read requestsQMC critical priority read requests QMC channel 0 high priority read requestsQMC channel 1 high priority read requestsQMC channel 2 high priority read requestsQMC high priority read requests Cycles DRAM channel 0 full with isochronous read requestsCycles DRAM channel 1 full with isochronous read requestsCycles DRAM channel 2 full with isochronous read requestsCycles DRAM channel 0 full with isochronous write requestsCycles DRAM channel 1 full with isochronous write requestsCycles DRAM channel 2 full with isochronous write requests IMC channel 0 isochronous read request occupancyIMC channel 1 isochronous read request occupancyIMC channel 2 isochronous read request occupancyIMC isochronous read request occupancy Cycles DRAM channel 0 full with normal read requestsCycles DRAM channel 1 full with normal read requestsCycles DRAM channel 2 full with normal read requestsCycles DRAM channel 0 full with normal write requestsCycles DRAM channel 1 full with normal write requestsCycles DRAM channel 2 full with normal write requests QMC channel 0 normal read requestsQMC channel 1 normal read requestsQMC channel 2 normal read requestsQMC normal read requests IMC channel 0 normal read request occupancyIMC channel 1 normal read request occupancyIMC channel 2 normal read request occupancyQMC channel 0 priority updatesQMC channel 1 priority updatesQMC channel 2 priority updatesQMC priority updates FULL_CH0QMC channel 0 full cache line writesFULL_CH1QMC channel 1 full cache line writesFULL_CH2QMC channel 2 full cache line writesFULL_ANYQMC full cache line writesPARTIAL_CH0QMC channel 0 partial cache line writesPARTIAL_CH1QMC channel 1 partial cache line writesPARTIAL_CH2QMC channel 2 partial cache line writesPARTIAL_ANYQMC partial cache line writes  8 STALLS_LINK_0Link 0 snoop stalls due to no PPT entrySTALLS_LINK_1Link 1 snoop stalls due to no PPT entryBUSY_LINK_0Cycles link 0 outbound header busyBUSY_LINK_1Cycles link 1 outbound header busyDRS_LINK_0Cycles QPI outbound link 0 DRS stalledNCB_LINK_0Cycles QPI outbound link 0 NCB stalledNCS_LINK_0Cycles QPI outbound link 0 NCS stalledDRS_LINK_1Cycles QPI outbound link 1 DRS stalledNCB_LINK_1Cycles QPI outbound link 1 NCB stalledNCS_LINK_1Cycles QPI outbound link 1 NCS stalledLINK_0Cycles QPI outbound link 0 multi flit stalledLINK_1Cycles QPI outbound link 1 multi flit stalled 8HOME_LINK_0Cycles QPI outbound link 0 HOME stalledSNOOP_LINK_0Cycles QPI outbound link 0 SNOOP stalledNDR_LINK_0Cycles QPI outbound link 0 NDR stalledHOME_LINK_1Cycles QPI outbound link 1 HOME stalledSNOOP_LINK_1Cycles QPI outbound link 1 SNOOP stalledNDR_LINK_1Cycles QPI outbound link 1 NDR stalledCycles QPI outbound link 0 single flit stalledCycles QPI outbound link 1 single flit stalled 8Local home snoop response - LLC does not have cache lineLocal home snoop response - LLC has cache line in S stateFWD_S_STATELocal home snoop response - LLC forwarding cache line in S state.FWD_I_STATELocal home snoop response - LLC has forwarded a modified cache lineCONFLICTLocal home conflict snoop responseWBLocal home snoop response - LLC has cache line in the M state Remote home snoop response - LLC does not have cache lineRemote home snoop response - LLC has cache line in S stateRemote home snoop response - LLC forwarding cache line in S state.Remote home snoop response - LLC has forwarded a modified cache lineRemote home conflict snoop responseRemote home snoop response - LLC has cache line in the M stateHITMRemote home snoop response - LLC HITM $UNC_CLK_UNHALTEDUncore clockticks.UNC_DRAM_OPENDRAM open comamnds issued for read or writeUNC_DRAM_PAGE_CLOSEDRAM page close due to idle timer expirationUNC_DRAM_PAGE_MISSUNC_DRAM_PRE_ALLUNC_DRAM_READ_CASUNC_DRAM_REFRESHUNC_DRAM_WRITE_CASUNC_GQ_ALLOCUNC_GQ_CYCLES_FULLUNC_GQ_CYCLES_NOT_EMPTYUNC_GQ_DATA_FROMCycles GQ data is importedUNC_GQ_DATA_TOCycles GQ data is exportedUNC_LLC_HITSUNC_LLC_LINES_INUNC_LLC_LINES_OUTUNC_LLC_MISSUNC_QHL_ADDRESS_CONFLICTSUNC_QHL_CONFLICT_CYCLESUNC_QHL_CYCLES_FULLUNC_QHL_CYCLES_NOT_EMPTYCycles QHL Tracker is not emptyUNC_QHL_FRC_ACK_CNFLTSUNC_QHL_OCCUPANCYCycles QHL Tracker Allocate to Deallocate Read OccupancyUNC_QHL_REQUESTSUNC_QHL_TO_QMC_BYPASSNumber of requests to QMC that bypass QHLUNC_QMC_BUSYCycles QMC busy with a read requestUNC_QMC_CANCELUNC_QMC_CRITICAL_PRIORITY_READSUNC_QMC_HIGH_PRIORITY_READSUNC_QMC_ISOC_FULLCycles DRAM full with isochronous (ISOC) read requestsUNC_IMC_ISOC_OCCUPANCYIMC isochronous (ISOC) Read OccupancyUNC_QMC_NORMAL_FULLCycles DRAM full with normal read requestsUNC_QMC_NORMAL_READSUNC_QMC_OCCUPANCYQMC OccupancyUNC_QMC_PRIORITY_UPDATESUNC_QMC_WRITESQMC cache line writesUNC_QPI_RX_NO_PPT_CREDITUNC_QPI_TX_HEADERUNC_QPI_TX_STALLED_MULTI_FLITCycles QPI outbound stallsUNC_QPI_TX_STALLED_SINGLE_FLITCycles QPI outbound link stallsUNC_SNP_RESP_TO_LOCAL_HOMELocal home snoop responseUNC_SNP_RESP_TO_REMOTE_HOMERemote home snoop response`abfced   $%!"3# &)0.-(+',*1/CBA@In the read tracker   @    IOH_ORDERDue to IOH ordering (write after read) conflictsREMOTE_ORDERDue to remote socket ordering (write after read) conflictsLOCAL_ORDERDue to local socket ordering (write after read) conflictsIOH_CONFLICTDue to IOH address conflictsREMOTE_CONFLICTDue to remote socket address conflictsLOCAL_CONFLICTDue to local socket address conflicts          Channel 0Channel 1Channel 2Any channel   8  8 8  $CORE_0Core 0CORE_1Core 1CORE_2Core 2CORE_3Core 3UNC_GC_OCCUPANCYNumber of queue entriesUNC_DRAM_THERMAL_THROTTLEDUncore cycles DRAM was throttled due to its temperature being above thermal throttling thresholdUNC_QHL_SLEEPSNumber of occurrences a request was put to sleepUNC_IMC_RETRYNumber of IMC DRAM channel retries (retries occur in RAS mode only)UNC_THERMAL_THROTTLING_TEMPUncore cycles that the PCU records core temperature above thresholdUNC_THERMAL_THROTTLED_TEMPUncore cycles that the PCU records that core is in power throttled state due to temperature being above thresholdUNC_PROCHOT_ASSERTIONNumber of system ssertions of PROCHOT indicating the entire processor has exceeded the thermal limitUNC_THERMAL_THROTTLING_PROCHOTUncore cycles that the PCU records that core is in power throttled state due PROCHOT assertionsUNC_TURBO_MODEUncore cycles that a core is operating in turbo modeUNC_CYCLES_UNHALTED_L3_FLL_ENABLEUncore cycles where at least one core is unhalted and all L3 ways are enabledUNC_CYCLES_UNHALTED_L3_FLL_DISABLEUncore cycles where at least one core is unhalted and all L3 ways are disabled`abfgced   $%!"34# &)0.-(+,*12/CBA@eedge leveliinvertccounter-mask in range [0-255]oqueue occupancypfmlib_intel_nhm_unc.c%s (%s.%d): exclusive unit mask group error %s (%s.%d): event does not support unit mask combination within a group :%s%s (%s.%d): raw umask is 8-bit wide %s (%s.%d): required modifiers missing: 0x%x %s:0x%x:%s=%lu[UNC_PERFEVTSEL=0x%lx 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unsigned intmax_encodingwsm_unc_unc_dram_page_missusel_res1usel_res2usel_res3usel_res4_flags2intel_x86_eflagwsm_unc_unc_dram_page_close_IO_read_baseget_event_nextpfm_wsm_unc_detectthis_unused2near_retPFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTwsm_unc_unc_imc_isoc_occupancyudescnhm_unc_unc_qmc_normal_fullPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000wsm_unc_unc_llc_missnhm_unc_unc_gq_cycles_not_emptypfm_dtype_tPFM_ATTR_UMASK_old_offsetwsm_unc_unc_gq_data_fromucodePFM_PMU_INTEL_IVB_EPwsm_unc_unc_dram_openintel_nhm_unc_supportwsm_unc_unc_qhl_conflict_cyclesPFM_PMU_I386_P6sel_event_selectPFM_PMU_PPC970MPos_detectnhm_unc_unc_qmc_critical_priority_readssvalPFM_PMU_GEN_IA64cpl_neq0PFM_PMU_I386_PMintel_wsm_unc_pelong long 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The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.DIVCounts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.CYCLES_DIV_BUSY:c=1:i=1:e=1MULCounts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD.BAD_TARGETBACLEAR asserted with bad target addressCLEARBACLEAR asserted, regardless of causeEARLYEarly Branch Prediciton Unit clearsLATELate Branch Prediction Unit clearsANYCount any Branch Prediction Unit clears Branch instructions executedCONDConditional branch instructions executedDIRECTUnconditional branches executedDIRECT_NEAR_CALLUnconditional call branches executedINDIRECT_NEAR_CALLIndirect call branches executedINDIRECT_NON_CALLIndirect non call branches executedNEAR_CALLSCall branches executedNON_CALLSAll non call branches executedRETURN_NEARIndirect return branches executedTAKENTaken branches executed  0@ALL_BRANCHESRetired branch instructions (Precise Event)CONDITIONALRetired conditional branch instructions (Precise Event)NEAR_CALLRetired near call instructions (Precise Event) Mispredicted branches executedMispredicted conditional branches executedMispredicted unconditional branches executedMispredicted non call branches executedMispredicted indirect call branches executedMispredicted indirect non call branches executedMispredicted call branches executedMispredicted return branches executedMispredicted taken branches executed  0@Counts mispredicted direct and indirect near unconditional retired calls L1DCycles L1D lockedL1D_L2Cycles L1D and L2 lockedTHREAD_PCycles when thread is not halted (programmable counter)REF_PReference base clock (133 Mhz) cycles when thread is not haltedTOTAL_CYCLESTotal number of elapsed cycles. Does not work when C-state enabledTHREAD_P:c=2:i=1 DTLB load missesPDE_MISSDTLB load miss caused by low part of addressWALK_COMPLETEDDTLB load miss page walks completeSTLB_HITDTLB second level hitPDP_MISSNumber of DTLB cache load misses where the high part of the linear to physical address translation was missedLARGE_WALK_COMPLETEDCounts number of completed large page walks due to load miss in the STLB @DTLB missesDTLB first level misses but second level hitDTLB miss page walksNumber of DTLB cache misses where the low part of the linear to physical address translation was missedNumber of DTLB misses where the high part of the linear to physical address translation was missedCounts number of completed large page walks due to misses in the STLB  @EPDE_MISSExtended Page Directory Entry missEPDPE_MISSExtended Page Directory Pointer missEPDPE_HITExtended Page Directory Pointer hitALLFloating point assists (Precise Event)INPUTFloating poiint assists for invalid input value (Precise Event)OUTPUTFloating point assists for invalid output value (Precise Event) MMXMMX UopsSSE_DOUBLE_PRECISIONSSE* FP double precision UopsSSE_FPSSE and SSE2 FP UopsSSE_FP_PACKEDSSE FP packed UopsSSE_FP_SCALARSSE FP scalar UopsSSE_SINGLE_PRECISIONSSE* FP single precision UopsSSE2_INTEGERSSE2 integer UopsX87Computational floating-point operations executed @All Floating Point to and from MMX transitionsTO_FPTransitions from MMX to Floating Point instructionsTO_MMXTransitions from Floating Point to MMX instructions FULLInstruction Fetche unit victim cache fullL1I_EVICTIONL1 Instruction cache evictionsAny Instruction Length Decoder stall cyclesIQ_FULL:LCP:MRU:REGENIQ_FULLInstruction Queue full stall cyclesLCPLength Change Prefix stall cyclesMRUStall cycles due to BPU MRU bypassREGENRegen stall cyclesDEC0Instructions that must be decoded by decoder 0 ANY_PInstructions Retired (Precise Event)Retired floating-point operations (Precise Event) M_EVICTL1D cache lines replaced in M stateM_REPLL1D cache lines allocated in the M stateM_SNOOP_EVICTL1D snoop eviction of cache lines in M stateREPLL1 data cache lines allocatedAll references to the L1 data cacheCACHEABLEL1 data cacheable reads and writesE_STATEL1 data cache read in E stateI_STATEL1 data cache read in I state (misses)M_STATEL1 data cache read in M stateMESIL1 data cache readsS_STATEL1 data cache read in S stateL1 data cache load locks in E stateHITL1 data cache load lock hitsL1 data cache load locks in M stateL1 data cache load locks in S stateL1 data cache stores in E stateL1 data cache store in the I stateL1 data cache stores in M stateL1 data cache stores in S stateL1 data cache store in all states MISSL1D hardware prefetch missesREQUESTSL1D hardware prefetch requestsTRIGGERSL1D hardware prefetch requests triggeredL1 writebacks to L2 in E stateL1 writebacks to L2 in I state (misses)L1 writebacks to L2 in M stateL1 writebacks to L2 in S stateAll L1 writebacks to L2 CYCLES_STALLEDL1I instruction fetch stall cyclesHITSL1I instruction fetch hitsMISSESL1I instruction fetch missesREADSL1I Instruction fetchesAll L2 data requestsDEMAND_E_STATEL2 data demand loads in E stateDEMAND_I_STATEL2 data demand loads in I state (misses)DEMAND_M_STATEL2 data demand loads in M stateDEMAND_MESIL2 data demand requestsDEMAND_S_STATEL2 data demand loads in S statePREFETCH_E_STATEL2 data prefetches in E statePREFETCH_I_STATEL2 data prefetches in the I state (misses)PREFETCH_M_STATEL2 data prefetches in M statePREFETCH_MESIAll L2 data prefetchesPREFETCH_S_STATEL2 data prefetches in the S state @ Count L2 HW prefetcher detector hitsALLOCCount L2 HW prefetcher allocationsDATA_TRIGGERCount L2 HW data prefetcher triggeredCODE_TRIGGERCount L2 HW code prefetcher triggeredDCA_TRIGGERCount L2 HW DCA prefetcher triggeredKICK_STARTCount L2 HW prefetcher kick started L2 lines alloacatedL2 lines allocated in the E stateL2 lines allocated in the S state L2 lines evictedDEMAND_CLEANL2 lines evicted by a demand requestDEMAND_DIRTYL2 modified lines evicted by a demand requestPREFETCH_CLEANL2 lines evicted by a prefetch requestPREFETCH_DIRTYL2 modified lines evicted by a prefetch request All L2 missesREFERENCESAll L2 requestsIFETCH_HITL2 instruction fetch hitsIFETCH_MISSL2 instruction fetch missesIFETCHESL2 instruction fetchesLD_HITL2 load hitsLD_MISSL2 load missesLOADSL2 requestsPREFETCH_HITL2 prefetch hitsPREFETCH_MISSL2 prefetch missesPREFETCHESAll L2 prefetchesRFO_HITL2 RFO hitsRFO_MISSL2 RFO missesRFOSL2 RFO requests 0@ All L2 transactionsFILLL2 fill transactionsIFETCHL2 instruction fetch transactionsL1D_WBL1D writeback to L2 transactionsLOADL2 Load transactionsPREFETCHL2 prefetch transactionsRFOL2 RFO transactionsWBL2 writeback to LLC transactions @LOCK_E_STATEL2 demand lock RFOs in E stateLOCK_I_STATEL2 demand lock RFOs in I state (misses)LOCK_S_STATEL2 demand lock RFOs in S stateLOCK_HITAll demand L2 lock RFOs that hit the cacheLOCK_M_STATEL2 demand lock RFOs in M stateLOCK_MESIAll demand L2 lock RFOsAll L2 demand store RFOs that hit the cacheRFO_I_STATEL2 demand store RFOs in I state (misses)RFO_E_STATEL2 demand store RFOs in the E state (exclusive)RFO_M_STATEL2 demand store RFOs in M stateRFO_MESIAll L2 demand store RFOsRFO_S_STATEL2 demand store RFOs in S state@ Large ITLB hit All loads dispatchedMOBLoads dispatched from the MOBRSLoads dispatched that bypass the MOBRS_DELAYEDLoads dispatched from stage 305 REFERENCELongest latency cache referenceLongest latency cache missOAACTIVECycles when uops were delivered by the LSDINACTIVECycles no uops were delivered by the LSDACTIVE:i=1 SMCSelf-Modifying Code detectedCYCLESCycles machine clear assertedMEM_ORDERExecution pipeline restart due to Memory ordering conflictsFUSION_ASSISTCounts the number of macro-fusion assistsDECODEDInstructions decodedFUSIONS_DECODEDMacro-fused instructions decodedRESETCounts memory disambiguation reset cyclesWATCHDOGCounts the number of times the memory disambiguation watchdog kicked inWATCH_CYCLESCounts the cycles that the memory disambiguation watchdog is activeLATENCY_ABOVE_THRESHOLDMemory instructions retired above programmed clocks, minimum threshold value is 3, (Precise Event and ldlat required)Instructions retired which contains a load (Precise Event)STORESInstructions retired which contains a store (Precise Event)DTLB_MISSRetired loads that miss the DTLB (Precise Event)HIT_LFBRetired loads that miss L1D and hit an previously allocated LFB (Precise Event)L1D_HITRetired loads that hit the L1 data cache (Precise Event)L2_HITRetired loads that hit the L2 cache (Precise Event)L3_MISSRetired loads that miss the L3 cache (Precise Event)LLC_MISSThis is an alias for L3_MISSL3_UNSHARED_HITRetired loads that hit valid versions in the L3 cache (Precise Event)LLC_UNSHARED_HITThis is an alias for L3_UNSHARED_HITOTHER_CORE_L2_HIT_HITMRetired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)@Retired stores that miss the DTLB (Precise Event) OTHER_CORE_L2_HITMLoad instructions retired that HIT modified data in sibling core (Precise Event)REMOTE_CACHE_LOCAL_HOME_HITLoad instructions retired remote cache HIT data source (Precise Event)REMOTE_DRAMLoad instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)LOCAL_DRAMLoad instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)L3_DATA_MISS_UNKNOWNLoad instructions retired where the memory reference missed L3 and data source is unknown (Model 46 only, Precise Event)UNCACHEABLELoad instructions retired where the memory reference missed L1, L2, L3 caches and to perform I/O (Model 46 only, Precise Event) All offcore requestsANY_READOffcore read requestsANY_RFOOffcore RFO requestsDEMAND_READ_CODECounts number of offcore demand code read requests. Does not count L2 prefetch requests.DEMAND_READ_DATAOffcore demand data read requestsDEMAND_RFOOffcore demand RFO requestsL1D_WRITEBACKOffcore L1 data cache writebacksUNCACHED_MEMCounts number of offcore uncached memory requests @ TPR_READSCounts number of TPR readsTPR_WRITESCounts number of TPR writesFLAGSFlag stall cyclesREGISTERSPartial register stall cyclesROB_READ_PORTROB read port stalls cyclesSCOREBOARDScoreboard stall cyclesAll RAT stall cyclesFPCWFPU control word write stall cyclesLoad buffer stall cyclesMXCSRMXCSR rename stall cyclesRS_FULLReservation Station full stall cyclesSTOREStore buffer stall cyclesOTHEROther Resource related stall cyclesROB_FULLROB full stall cyclesResource related stall cycles @ PACK128 bit SIMD integer pack operationsPACKED_ARITH128 bit SIMD integer arithmetic operationsPACKED_LOGICAL128 bit SIMD integer logical operationsPACKED_MPY128 bit SIMD integer multiply operationsPACKED_SHIFT128 bit SIMD integer shift operationsSHUFFLE_MOVE128 bit SIMD integer shuffle/move operationsUNPACK128 bit SIMD integer unpack operations @SIMD integer 64 bit pack operationsSIMD integer 64 bit arithmetic operationsSIMD integer 64 bit logical operationsSIMD integer 64 bit packed multiply operationsSIMD integer 64 bit shift operationsSIMD integer 64 bit shuffle/move operationsSIMD integer 64 bit unpack operations @Thread responded HIT to snoopHITEThread responded HITE to snoopHITMThread responded HITM to snoopPROMOTIONCounts the number of L2 secondary misses that hit the Super QueuePROMOTION_POST_GOCounts the number of L2 secondary misses during the Super Queue filling L2LRU_HINTSCounts number of Super Queue LRU hints sent to L3FILL_DROPPEDCounts the number of SQ L2 fills dropped due to L2 busySPLIT_LOCKSuper Queue lock splits across a cache lineNTAStreaming SIMD L1D NTA prefetch missPACKED_DOUBLESIMD Packed-Double Uops retired (Precise Event)PACKED_SINGLESIMD Packed-Single Uops retired (Precise Event)SCALAR_DOUBLESIMD Scalar-Double Uops retired (Precise Event)SCALAR_SINGLESIMD Scalar-Single Uops retired (Precise Event)VECTOR_INTEGERSIMD Vector Integer Uops retired (Precise Event)AT_RETLoads delayed with at-Retirement block codeL1D_BLOCKCacheable loads delayed with L1D block codeNOT_STALoads delayed due to a store blocked for unknown dataSTALoads delayed due to a store blocked for an unknown addressESP_FOLDINGStack pointer instructions decodedESP_SYNCStack pointer sync operationsMSUops decoded by Microcode SequencerMS_CYCLES_ACTIVECycles in which at least one uop is decoded by Microcode SequencerMS:c=1PORT0Uops executed on port 0PORT1Uops executed on port 1PORT2_COREUops executed on port 2 on any thread (core count only)PORT3_COREUops executed on port 3 on any thread (core count only)PORT4_COREUops executed on port 4 on any thread (core count only)PORT5Uops executed on port 5PORT015Uops issued on ports 0, 1 or 5PORT234_COREUops issued on ports 2, 3 or 4 on any thread (core count only)PORT015_STALL_CYCLESCycles no Uops issued on ports 0, 1 or 5PORT015:c=1:i=1      @  @Uops issuedSTALLED_CYCLESCycles stalled no issued uopsANY:c=1:i=1FUSEDFused Uops issued Uops retired (Precise Event)RETIRE_SLOTSRetirement slots used (Precise Event)ACTIVE_CYCLESCycles Uops are being retired (Precise Event)ANY:c=1STALL_CYCLESCycles No Uops retired (Precise Event)MACRO_FUSEDMacro-fused Uops retired (Precise Event) DMND_DATA_RDRequest: counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFODMND_IFETCHRequest: counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesRequest: counts the number of writeback (modified to exclusive) transactionsPF_DATA_RDRequest: counts the number of data cacheline reads generated by L2 prefetchersPF_RFORequest: counts the number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: counts the number of code reads generated by L2 prefetchersRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCHPF_IFETCH:DMND_IFETCHANY_REQUESTRequest: combination of all requests umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:OTHERANY_DATARequest: any data read/write requestDMND_DATA_RD:PF_DATA_RD:DMND_RFO:PF_RFOANY_DATA_RDRequest: any data read in requestDMND_DATA_RD:PF_DATA_RDRequest: combination of DMND_RFO | PF_RFODMND_RFO:PF_RFOUNCORE_HITResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)OTHER_CORE_HIT_SNPResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)OTHER_CORE_HITMResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)REMOTE_CACHE_HITMResponse: counts L3 Hit: local or remote home requests that hit a remote L3 cacheline in modified (HITM) stateREMOTE_CACHE_FWDResponse: counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)Response: counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAMResponse: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAMNON_DRAMResponse: Non-DRAM requests that were serviced by IOHANY_CACHE_DRAMResponse: requests serviced by any source but IOHUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAMANY_DRAMResponse: requests serviced by local or remote DRAMREMOTE_DRAM:LOCAL_DRAMANY_LLC_MISSResponse: requests that missed in L3REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMLOCAL_CACHE_DRAMResponse: requests hit local core or uncore caches or local DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:LOCAL_DRAMREMOTE_CACHE_DRAMResponse: requests that miss L3 and hit remote caches or DRAMREMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAMANY_RESPONSEResponse: combination of all response umasksUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAM:NON_DRAM @D 3" @`G8 UNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)INSTRUCTION_RETIREDCount the number of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDUNHALTED_REFERENCE_CYCLESUnhalted reference cyclesLLC_REFERENCESCount each request originating equiv the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESILAST_LEVEL_CACHE_REFERENCESThis is an alias for LLC_REFERENCESLLC_MISSESCount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATELAST_LEVEL_CACHE_MISSESThis is an equiv for LLC_MISSESBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.BR_INST_RETIRED:ALL_BRANCHESARITHCounts arithmetic multiply and divide operationsBACLEARBranch address calculatorBACLEAR_FORCE_IQInstruction queue forced BACLEARBOGUS_BRCounts the number of bogus branches.BPU_CLEARSBranch prediction Unit clearsBPU_MISSED_CALL_RETBranch prediction unit missed call or returnBR_INST_DECODEDBranch instructions decodedBR_INST_EXECBR_INST_RETIREDRetired branch instructionsBR_MISP_EXECBR_MISP_RETIREDCount Mispredicted Branch ActivityCACHE_LOCK_CYCLESCache lock cyclesCPU_CLK_UNHALTEDCycles when processor is not in halted stateDTLB_LOAD_MISSESData TLB load missesDTLB_MISSESData TLB missesEPTExtended Page DirectoryES_REG_RENAMESES segment renamesFP_ASSISTFloating point assistsFP_COMP_OPS_EXEFloating poing computational micro-opsFP_MMX_TRANSFloating Point to and from MMX transitionsIFU_IVCInstruction Fetch unit victim cacheILD_STALLInstruction Length Decoder stallsINST_DECODEDINST_QUEUE_WRITESInstructions written to instruction queue.INST_QUEUE_WRITE_CYCLESCycles instructions are written to the instruction queueINST_RETIREDInstructions retiredIO_TRANSACTIONSI/O transactionsITLB_FLUSHCounts the number of ITLB flushesITLB_MISSESInstruction TLB missesITLB_MISS_RETIREDRetired instructions that missed the ITLB (Precise Event)L1D cacheL1D_ALL_REFL1D referencesL1D_CACHE_LDL1D cacheable loads. WARNING: event may overcount loadsL1D_CACHE_LOCKL1 data cache load lockL1D_CACHE_LOCK_FB_HITL1D load lock accepted in fill bufferL1D_CACHE_PREFETCH_LOCK_FB_HITL1D prefetch load lock accepted in fill bufferL1D_CACHE_STL1 data cache storesL1D_PREFETCHL1D hardware prefetchL1D_WB_L2L1 writebacks to L2L1IL1I instruction fetchesL1I_OPPORTUNISTIC_HITSOpportunistic hits in streamingL2_DATA_RQSTSL2 data requestsL2_HW_PREFETCHL2 HW prefetchesL2_LINES_INL2_LINES_OUTL2_RQSTSL2_TRANSACTIONSL2 transactionsL2_WRITEL2 demand lock/store RFOLARGE_ITLBLarge instruction TLBLOAD_DISPATCHLoads dispatchedLOAD_HIT_PRELoad operations conflicting with software prefetchesLONGEST_LAT_CACHELSDLoop stream detectorMACHINE_CLEARSMachine ClearMACRO_INSTSMacro-fused instructionsMEMORY_DISAMBIGUATIONMemory Disambiguation ActivityMEM_INST_RETIREDMemory instructions retiredMEM_LOAD_RETIREDRetired loadsMEM_STORE_RETIREDRetired storesMEM_UNCORE_RETIREDLoad instructions retired which hit offcoreOFFCORE_REQUESTSOffcore memory requestsOFFCORE_REQUESTS_SQ_FULLCounts cycles the Offcore Request buffer or Super Queue is full.PARTIAL_ADDRESS_ALIASFalse dependencies due to partial address fromingPIC_ACCESSESProgrammable interrupt controllerRAT_STALLSRegister allocation table stallsRESOURCE_STALLSProcessor stallsSEG_RENAME_STALLSSegment rename stall cyclesSEGMENT_REG_LOADSCounts number of segment register loadsSIMD_INT_128128 bit SIMD integer operationsSIMD_INT_6464 bit SIMD integer operationsSNOOP_RESPONSESnoopSQ_FULL_STALL_CYCLESCounts cycles the Offcore Request buffer or Super Queue is full and request(s) are outstanding.SQ_MISCSuper Queue Activity Related to L2 Cache AccessSSE_MEM_EXECStreaming SIMD executedSSEX_UOPS_RETIREDSIMD micro-ops retiredSTORE_BLOCKSDelayed loadsTWO_UOP_INSTS_DECODEDTwo micro-ops instructions decodedUOPS_DECODED_DEC0Micro-ops decoded by decoder 0UOPS_DECODEDMicro-ops decodedUOPS_EXECUTEDMicro-ops executedUOPS_ISSUEDMicro-ops issuedUOPS_RETIREDMicro-ops retiredUOP_UNFUSIONMicro-ops unfusions due to FP exceptionsOFFCORE_RESPONSE_0Offcore response 0 (must provide at least one request and one response umasks)<???#.O?.O?.A?.A????????? ?? ??c?<??I?O???????????l??? ?Q?C?@?B?S?R?A?N?(???& ????$??' ???L?.???? ?  ? ???????????????K????=? ???? ?unknown L3 cache missminimal latency core cache hit. Request was satisfied by L1 data cachepending core cache HIT. Outstanding core cache miss to same cacheline address already underwaydata request satisfied by the L2L3 HIT. Local or remote home request that hit L3 in the uncore with no coherency actions required (snooping)L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where no modified copy was found (clean)L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where modified copies were found (HITM)reservedL3 MISS. Local homed request that missed L3 and was serviced by forwarded data following a cross package snoop where no modified copy was found (remote home requests are not counted)L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to shared state)L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to shared state)L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to exclusive state)L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to exclusive state)request to uncacheable memoryIntel NehalemnhmIntel Nehalem EXnhm_ex int^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;H Y { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  @ W W W W  #&W$&H%ret(W\#=W$=X%ret?Wl&RW$Rh'v'(valvWl Y 7 {) L ' Y a {) 1v Q) > ' Y  { ) P )  ')   Y  {)  ) 2 Q) L ' Y a {) v Q*  Q* 6 '* H ' Y  {* Z *   '* ( Q Y = {* S -* n *  Q Y  {*  *  Q*  -*  * )  -* E; '* WV -* sq  Y  { *  v*  Q*  '*  - Y  { *  * \3  Y H { * ^ 8* y *  *  Q*  Q*  *  Q* $ '* 66 ' Y K {* Ha ;* z| *  Q*  *  Q*  -*   Y  {* . * CI * id '* { -*  *  -*  *  *  ;* ! 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&˃gZv'r$YxgZvr$Y2Y!.ufgvcntmskpfm_intel_x86_cfgufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEintel_nhm_support_IO_save_endPFM_PMU_AMD64nhm_l1d_prefetchPFM_PMU_MIPS_SB1nhm_br_inst_retiredpfm_nhm_ex_detect_IO_write_basePFM_PMU_SPARC_NIAGARA2nhm_dtlb_missesPFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intnhm_snoop_responsePFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kintel_x86_mods_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1nhm_fp_comp_ops_exengrpPFM_DTYPE_MAXnhm_mem_inst_retiredpfm_event_info_tuequivnhm_simd_int_64PFM_PMU_PPC970ucntmsknhm_l1d_cache_lockPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCnhm_br_inst_execPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXnhm_ssex_uops_retiredctrlPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000charmodelnhm_mem_uncore_retireddfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tnhm_fp_mmx_transPFM_PMU_POWER5pname_IO_lock_tnhm_uops_executedPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERpfm_nhm_initPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrnhm_uops_decodedattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markerspfm_nhm_detectnhm_dtlb_load_missesPFM_ATTR_MAXnhm_arithPFM_PMU_MIPS_VR5432pfm_event_attr_info_tnhm_l2_lines_inmodmsk_reqdfl_val64nhm_ild_stallmodhwnhm_offcore_response_0PFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176nhm_l2_writePFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intnhm_cache_lock_cyclesmax_encoding_flags2nhm_l1dnhm_l1i_IO_read_basenhm_longest_lat_cacheget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescnhm_offcore_requestsPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPnhm_inst_decodedintel_nhm_pepfmlib_intel_nhm.cPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectnhm_uops_retiredsvalPFM_PMU_GEN_IA64nhm_mem_load_retiredPFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endPFM_PMU_INTEL_PPROumasksnhm_baclearnhm_simd_int_128npattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5nhm_fp_assist_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOnhm_lsdnhm_l1d_all_refget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modenhm_l2_data_rqstspfm_attr_ctrl_tPFM_PMU_COREDUOfamilynhm_load_dispatchPFM_PMU_INTEL_WSM_UNCfstrnhm_l2_transactionspfmlib_pmuPFM_PMU_TYPE_COREintel_nhm_ex_supportPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnhm_uops_issuednhm_inst_retirednum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMnhm_sse_mem_execsteppingcan_auto_encodeget_event_attr_infonhm_l2_rqstssizelong long unsigned intnhm_sq_miscpfm_nhm_data_src_descPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tnhm_l2_lines_outPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64nhm_memory_disambiguationPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9nhm_bpu_clearsperf_nameis_dflnhm_l1d_cache_stPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12nhm_br_misp_retiredPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3nhm_ifu_ivc_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descnhm_eptPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREnhm_l1d_wb_l2_next__off64_tcodenhm_rat_stallsdtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Iosidnhm_l2_hw_prefetchPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMnhm_br_misp_execpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsarch_versionnhm_l1d_cache_ldPFM_PMU_INTEL_SNBEP_UNC_PCUnhm_mem_store_retirednhm_resource_stallsPFM_OS_MAX_IO_read_endpfm_intel_x86_config_tnhm_machine_clearsmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenonhm_macro_instsreservednhm_pic_accessesPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsnhm_cpu_clk_unhaltedPFM_PMU_ITANIUM2nhm_store_blocksPFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regnhm_large_itlbpfm_os_tsupported_plmpfmlib_event_desc_tdata_src_encodingsGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx  mAC Ec @KAC F `AC T  )AC d .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @#+@ &$1; 6)@SH C}x*Tag30bx0 {cv 0e0P -}  `  P 1`*9 J ^  oP@`@ `#$@&( (P9(J@*@R+b@-s/@13@57@:p`?ACF`@L%Q2TPAU@S`WiXqZ@[ ]@_bePil`o+p:sNw0_{0o} P @`@ p!@.m=mKO\   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LK8 LD LP L \ Lh L t L L L L: L L L& L2 L$ LI LI L A L> L6 L LM L L" L  L L  Ly% L1 LL= L@ Z L m Ldy L> L  L L L L L L) L L$ L L L ( L4 LA LL LV^mm L  Lm L  L L  L* 8 LD`b L+ n| L' LL L  L  L L *@8 LDb Ln`| L LC@ L  L  LC`# L $> L>K@&Y L f (t Lh( L @* L + L@- L*/  LG1& L33A LzN@5\ L i7 Lh : L`? LA LC LF L +@LI LK VQd LqT L U L `W L X LZ L[ L ]! L.@_L LU Ybg L?te Li LS l L`o Lp LUs L7 &w4 LA{O L\}j Lw  L L L  L` Lt  LX' L. 4R LR_} L  LR L]S L ` L L HO Dmd/308 1386324440 1009 1009 100664 107992 ` ELF> @@UHH H}E}tE*t%tUHH H}E}tE/t,t /tUHH}]4[ 5[ ESP_FOLDINGStack pointer instructions decodedESP_SYNCStack pointer sync operationsMSCounts the number of uops decoded by the Microcode Sequencer (MS). The MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring.MS_CYCLES_ACTIVEUops decoded by Microcode SequencerMS:c=1STALL_CYCLESCycles no Uops are decodedEARLYEarly Branch Prediction Unit clearsLATELate Branch Prediction Unit clearsANYUops retired (Precise Event)MACRO_FUSEDMacro-fused Uops retired (Precise Event)RETIRE_SLOTSRetirement slots used (Precise Event)Cycles Uops are not retiring (Precise Event)ANY:c=1:i=1TOTAL_CYCLESTotal cycles using precise uop retired event (Precise Event)ANY:c=16:i=1ACTIVE_CYCLESAlias for TOTAL_CYCLES (Precise Event) ALL_BRANCHESMispredicted retired branch instructions (Precise Event)NEAR_CALLMispredicted near retired calls (Precise Event)CONDITIONALMispredicted conditional branches retired (Precise Event)WALK_CYCLESExtended Page Table walk cycles PORT0Uops executed on port 0 (integer arithmetic, SIMD and FP add uops)PORT1Uops executed on port 1 (integer arithmetic, SIMD, integer shift, FP multiply, FP divide uops)PORT2_COREUops executed on port 2 on any thread (load uops) (core count only)PORT3_COREUops executed on port 3 on any thread (store uops) (core count only)PORT4_COREUops executed on port 4 on any thread (handle store values for stores on port 3) (core count only)PORT5Uops executed on port 5PORT015Uops issued on ports 0, 1 or 5PORT234_COREUops issued on ports 2, 3 or 4 on any thread (core count only)PORT015_STALL_CYCLESCycles no Uops issued on ports 0, 1 or 5PORT015:c=1:i=1CORE_ACTIVE_CYCLES_NO_PORT5Cycles in which uops are executed only on port0-4 on any thread (core count only)CORE_ACTIVE_CYCLESCycles in which uops are executed on any port any thread (core count only)CORE_STALL_CYCLESCycles in which no uops are executed on any port any thread (core count only)CORE_STALL_CYCLES_NO_PORT5Cycles in which no uops are executed on any port0-4 on any thread (core count only)CORE_STALL_COUNTNumber of transitions from stalled to uops to execute on any port any thread (core count only)CORE_STALL_CYCLES:e=1CORE_STALL_COUNT_NO_PORT5Number of transitions from stalled to uops to execute on port0-4 on any thread (core count only)CORE_STALL_CYCLES_NO_PORT5:e=1      @  @ 0? 0?88?ANY_PInstructions Retired (Precise Event)X87Retired floating-point operations (Precise Event)MMXRetired MMX instructions (Precise Event)Total cycles (Precise Event)ANY_P:c=16:i=1 Any Instruction Length Decoder stall cyclesIQ_FULL:LCP:MRU:REGENIQ_FULLInstruction Queue full stall cyclesLCPLength Change Prefix stall cyclesMRUStall cycles due to BPU MRU bypassREGENRegen stall cyclesDTLB load missesPDE_MISSDTLB load miss caused by low part of addressSTLB_HITDTLB second level hitWALK_COMPLETEDDTLB load miss page walks completeDTLB load miss page walk cycles L2 lines alloacatedE_STATEL2 lines allocated in the E stateS_STATEL2 lines allocated in the S state PACKED_DOUBLESIMD Packed-Double Uops retired (Precise Event)PACKED_SINGLESIMD Packed-Single Uops retired (Precise Event)SCALAR_DOUBLESIMD Scalar-Double Uops retired (Precise Event)SCALAR_SINGLESIMD Scalar-Single Uops retired (Precise Event)VECTOR_INTEGERSIMD Vector Integer Uops retired (Precise Event)AT_RETLoads delayed with at-Retirement block codeL1D_BLOCKCacheable loads delayed with L1D block codeAll Floating Point to and from MMX transitionsTO_FPTransitions from MMX to Floating Point instructionsTO_MMXTransitions from Floating Point to MMX instructions L1DCycles L1D lockedL1D_L2Cycles L1D and L2 lockedMISSLast level cache missREFERENCELast level cache referencePACKSIMD integer 64 bit pack operationsPACKED_ARITHSIMD integer 64 bit arithmetic operationsPACKED_LOGICALSIMD integer 64 bit logical operationsPACKED_MPYSIMD integer 64 bit packed multiply operationsPACKED_SHIFTSIMD integer 64 bit shift operationsSHUFFLE_MOVESIMD integer 64 bit shuffle/move operationsUNPACKSIMD integer 64 bit unpack operations @Mispredicted branches executedCONDMispredicted conditional branches executedDIRECTMispredicted unconditional branches executedDIRECT_NEAR_CALLMispredicted non call branches executedINDIRECT_NEAR_CALLMispredicted indirect call branches executedINDIRECT_NON_CALLMispredicted indirect non call branches executedNEAR_CALLSMispredicted call branches executedNON_CALLSRETURN_NEARMispredicted return branches executedTAKENMispredicted taken branches executed 0@BAD_TARGETBACLEAR asserted with bad target addressCLEARBACLEAR asserted, regardless of causeDTLB missesLARGE_WALK_COMPLETEDDTLB miss large page walksDTLB first level misses but second level hitDTLB miss page walksDTLB miss page walk cycles LATENCY_ABOVE_THRESHOLDMemory instructions retired above programmed clocks, minimum threshold value is 3, (Precise Event and ldlat required)LOADSInstructions retired which contains a load (Precise Event)STORESInstructions retired which contains a store (Precise Event)Uops issuedCycles stalled no issued uopsFUSEDFused Uops issuedCYCLES_ALL_THREADSCycles uops issued on either threads (core count)ANY:c=1:t=1Cycles no uops issued on any threads (core count)ANY:c=1:i=1:t=1  IFETCH_HITL2 instruction fetch hitsIFETCH_MISSL2 instruction fetch missesIFETCHESL2 instruction fetchesLD_HITL2 load hitsLD_MISSL2 load missesL2 requestsAll L2 missesPREFETCH_HITL2 prefetch hitsPREFETCH_MISSL2 prefetch missesPREFETCHESAll L2 prefetchesREFERENCESAll L2 requestsRFO_HITL2 RFO hitsRFO_MISSL2 RFO missesRFOSL2 RFO requests 0@ All loads dispatchedRSNumber of loads dispatched from the Reservation Station (RS) that bypass the Memory Order BufferRS_DELAYEDNumber of delayed RS dispatches at the stage latchMOBNumber of loads dispatched from Reservation Station (RS) CODESnoop code requestsDATASnoop data requestsINVALIDATESnoop invalidate requestsAll offcore requestsANY_READOffcore read requestsANY_RFOOffcore RFO requestsDEMAND_READ_CODEOffcore demand code read requestsDEMAND_READ_DATAOffcore demand data read requestsDEMAND_RFOOffcore demand RFO requestsL1D_WRITEBACKOffcore L1 data cache writebacks @OVERLAP_STORELoads that partially overlap an earlier store STOREStore referenced with misaligned address MEM_ORDERExecution pipeline restart due to Memory ordering conflicts CYCLESCycles machine clear is assertedSMCSelf-modifying code detectedMMX UopsSSE_DOUBLE_PRECISIONSSE FP double precision UopsSSE_FPSSE and SSE2 FP UopsSSE_FP_PACKEDSSE FP packed UopsSSE_FP_SCALARSSE FP scalar UopsSSE_SINGLE_PRECISIONSSE FP single precision UopsSSE2_INTEGERSSE2 integer UopsComputational floating-point operations executed @Retired branch instructions (Precise Event)Retired conditional branch instructions (Precise Event)Retired near call instructions (Precise Event) HITLarge ITLB hit UOPSCounts the number of micro-ops delivered by LSDACTIVECycles is which at least one micro-op delivered by LSDUOPS:c=1INACTIVECycles is which no micro-op is delivered by LSDUOPS:c=1:i=1L2 lines evictedDEMAND_CLEANL2 lines evicted by a demand requestDEMAND_DIRTYL2 modified lines evicted by a demand requestPREFETCH_CLEANL2 lines evicted by a prefetch requestPREFETCH_DIRTYL2 modified lines evicted by a prefetch request ITLB missITLB miss page walksITLB miss page walk cyclesNumber of completed large page walks due to misses in the STLBITLB misses hitting second level TLB L1D hardware prefetch missesREQUESTSL1D hardware prefetch requestsTRIGGERSL1D hardware prefetch requests triggeredLRU_HINTSSuper Queue LRU hints sent to LLCSPLIT_LOCKSuper Queue lock splits across a cache lineALLAll X87 Floating point assists (Precise Event)INPUTX87 Floating point assists for invalid input value (Precise Event)OUTPUTX87 Floating point assists for invalid output value (Precise Event) 128 bit SIMD integer pack operations128 bit SIMD integer arithmetic operations128 bit SIMD integer logical operations128 bit SIMD integer multiply operations128 bit SIMD integer shift operations128 bit SIMD integer shuffle/move operations128 bit SIMD integer unpack operations @Outstanding offcore readsOutstanding offcore demand code readsOutstanding offcore demand data readsOutstanding offcore demand RFOsDTLB_MISSRetired stores that miss the DTLB (Precise Event) DEC0Instructions that must be decoded by decoder 0 DECODEDInstructions decoded CYCLES_DIV_BUSYCounts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is onDIVCounts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is onCYCLES_DIV_BUSY:c=1:i=1:e=1MULCounts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect when HT is onAll L2 transactionsFILLL2 fill transactionsIFETCHL2 instruction fetch transactionsL1D_WBL1D writeback to L2 transactionsLOADL2 Load transactionsPREFETCHL2 prefetch transactionsRFOL2 RFO transactionsWBL2 writeback to LLC transactions @All Store buffer stall cycles LOCAL_HITMLoad instructions retired that HIT modified data in sibling core (Precise Event)LOCAL_DRAM_AND_REMOTE_CACHE_HITLoad instructions retired local dram and remote cache HIT data sources (Precise Event)REMOTE_DRAMLoad instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)UNCACHEABLELoad instructions retired IO (Precise Event)REMOTE_HITMRetired loads that hit remote socket in modified state (Precise Event)OTHER_LLC_MISSLoad instructions retired other LLC miss (Precise Event)UNKNOWN_SOURCELoad instructions retired unknown LLC miss (Precise Event)LOCAL_DRAMRetired loads with a data source of local DRAM or locally homed remote cache HITM (Precise Event)OTHER_CORE_L2_HITMRetired loads instruction that hit modified data in sibling core (Precise Event)REMOTE_CACHE_LOCAL_HOME_HITRetired loads instruction that hit remote cache hit data source (Precise Event)Retired loads instruction remote DRAM and remote home-remote cache HITM (Precise Event)5555 55444 4All L2 data requestsDEMAND_E_STATEL2 data demand loads in E stateDEMAND_I_STATEL2 data demand loads in I state (misses)DEMAND_M_STATEL2 data demand loads in M stateDEMAND_MESIL2 data demand requestsDEMAND_S_STATEL2 data demand loads in S statePREFETCH_E_STATEL2 data prefetches in E statePREFETCH_I_STATEL2 data prefetches in the I state (misses)PREFETCH_M_STATEL2 data prefetches in M statePREFETCH_MESIAll L2 data prefetchesPREFETCH_S_STATEL2 data prefetches in the S state @ Branch instructions executedConditional branch instructions executedUnconditional branches executedUnconditional call branches executedIndirect call branches executedIndirect non call branches executedCall branches executedAll non call branches executedIndirect return branches executedTaken branches executed  0@Outstanding snoop code requestsCODE_NOT_EMPTYCycles snoop code requests queue not emptyCODE:c=1Outstanding snoop data requestsDATA_NOT_EMPTYCycles snoop data requests queue not emptyDATA:c=1Outstanding snoop invalidate requestsINVALIDATE_NOT_EMPTYCycles snoop invalidate requests queue not emptyINVALIDATE:c=1Retired loads that miss the DTLB (Precise Event)HIT_LFBRetired loads that miss L1D and hit an previously allocated LFB (Precise Event)L1D_HITRetired loads that hit the L1 data cache (Precise Event)L2_HITRetired loads that hit the L2 cache (Precise Event)L3_MISSRetired loads that miss the LLC cache (Precise Event)LLC_MISSThis is an alias for L3_MISSL3_UNSHARED_HITRetired loads that hit valid versions in the LLC cache (Precise Event)LLC_UNSHARED_HITThis is an alias for L3_UNSHARED_HITOTHER_CORE_L2_HIT_HITMRetired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)@CYCLES_STALLEDL1I instruction fetch stall cyclesHITSL1I instruction fetch hitsMISSESL1I instruction fetch missesREADSL1I Instruction fetchesLOCK_E_STATEL2 demand lock RFOs in E stateLOCK_HITAll demand L2 lock RFOs that hit the cacheLOCK_I_STATEL2 demand lock RFOs in I state (misses)LOCK_M_STATEL2 demand lock RFOs in M stateLOCK_MESIAll demand L2 lock RFOsLOCK_S_STATEL2 demand lock RFOs in S stateAll L2 demand store RFOs that hit the cacheRFO_I_STATEL2 demand store RFOs in I state (misses)RFO_M_STATEL2 demand store RFOs in M stateRFO_MESIAll L2 demand store RFOsRFO_S_STATEL2 demand store RFOs in S state@ Thread responded HIT to snoopHITEThread responded HITE to snoopHITMThread responded HITM to snoopM_EVICTL1D cache lines replaced in M state M_REPLL1D cache lines allocated in the M stateM_SNOOP_EVICTL1D snoop eviction of cache lines in M stateREPLL1 data cache lines allocatedResource related stall cyclesFPCWFPU control word write stall cyclesLoad buffer stall cyclesMXCSRMXCSR rename stall cyclesOTHEROther Resource related stall cyclesROB_FULLROB full stall cyclesRS_FULLReservation Station full stall cyclesStore buffer stall cycles @All RAT stall cyclesFLAGS:REGISTERS:ROB_READ_PORT:SCOREBOARDFLAGSFlag stall cyclesREGISTERSPartial register stall cyclesROB_READ_PORTROB read port stalls cyclesSCOREBOARDScoreboard stall cycles THREAD_PCycles when thread is not halted (programmable counter)REF_PReference base clock (133 Mhz) cycles when thread is not haltedTotal number of elapsed cycles. Does not work when C-state enabledTHREAD_P:c=2:i=1L1 writebacks to L2 in E stateI_STATEL1 writebacks to L2 in I state (misses)M_STATEL1 writebacks to L2 in M stateMESIAll L1 writebacks to L2L1 writebacks to L2 in S stateDMND_DATA_RDRequest: counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFODMND_IFETCHRequest: counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesRequest: counts the number of writeback (modified to exclusive) transactionsPF_DATA_RDRequest: counts the number of data cacheline reads generated by L2 prefetchersPF_RFORequest: counts the number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: counts the number of code reads generated by L2 prefetchersRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCHPF_IFETCH:DMND_IFETCHANY_REQUESTRequest: combination of all requests umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:OTHERANY_DATARequest: any data read/write requestDMND_DATA_RD:PF_DATA_RD:DMND_RFO:PF_RFOANY_DATA_RDRequest: any data read in requestDMND_DATA_RD:PF_DATA_RDRequest: combination of DMND_RFO | PF_RFODMND_RFO:PF_RFOUNCORE_HITResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)OTHER_CORE_HIT_SNPResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)OTHER_CORE_HITMResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)REMOTE_CACHE_HITMResponse: counts L3 Hit: local or remote home requests that hit a remote L3 cacheline in modified (HITM) stateREMOTE_CACHE_FWDResponse: counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)Response: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM or a remote cacheResponse: counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAMResponse: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAMResponse: counts L3 Miss: remote home requests that missed the L3 cacheNON_DRAMResponse: Non-DRAM requests that were serviced by IOHANY_CACHE_DRAMResponse: requests serviced by any source but IOHUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:OTHER_LLC_MISS:REMOTE_DRAM:LOCAL_DRAM_AND_REMOTE_CACHE_HITANY_DRAMResponse: requests serviced by local or remote DRAMREMOTE_DRAM:LOCAL_DRAMANY_LLC_MISSResponse: requests that missed in L3REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMREMOTE_CACHE_HITM:REMOTE_DRAM:OTHER_LLC_MISS:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:NON_DRAMLOCAL_CACHE_DRAMResponse: requests hit local core or uncore caches or local DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:LOCAL_DRAMREMOTE_CACHE_DRAMResponse: requests that miss L3 and hit remote caches or DRAMREMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAMLOCAL_CACHEResponse: any local (core and socket) cachesUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITMANY_RESPONSEResponse: combination of all response umasksUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:REMOTE_DRAM:OTHER_LLC_MISS:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:NON_DRAM @D 3"45 5 4@4@545`445'4X4 4 5UNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted).INSTRUCTION_RETIREDCount the number of instructions at retirement.INSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDUNHALTED_REFERENCE_CYCLESUnhalted reference cyclesLLC_REFERENCESCount each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch (Alias for L3_LAT_CACHE:REFERENCE).L3_LAT_CACHE:REFERENCELAST_LEVEL_CACHE_REFERENCESThis is an alias for L3_LAT_CACHE:REFERENCELLC_MISSESCount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch (Alias for L3_LAT_CACHE:MISS)L3_LAT_CACHE:MISSLAST_LEVEL_CACHE_MISSESThis is an alias for L3_LAT_CACHE:MISSBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.BR_INST_RETIRED:ALL_BRANCHESUOPS_DECODEDMicro-ops decodedL1D_CACHE_LOCK_FB_HITL1D cacheable load lock speculated or retired accepted into the fill bufferBPU_CLEARSBranch Prediction Unit clearsUOPS_RETIREDCycles Uops are being retired (Precise Event)BR_MISP_RETIREDMispredicted retired branches (Precise Event)EPTExtended Page TableUOPS_EXECUTEDMicro-ops executedIO_TRANSACTIONSI/O transactionsES_REG_RENAMESES segment renamesINST_RETIREDInstructions retired (Precise Event)ILD_STALLInstruction Length Decoder stallsDTLB_LOAD_MISSESL2_LINES_INSSEX_UOPS_RETIREDSIMD micro-ops retired (Precise Event)STORE_BLOCKSLoad delayed by block codeFP_MMX_TRANSFloating Point to and from MMX transitionsCACHE_LOCK_CYCLESCache lockedOFFCORE_REQUESTS_SQ_FULLOffcore requests blocked due to Super Queue fullL3_LAT_CACHELast level cache accessesSIMD_INT_64SIMD 64-bit integer operationsBR_INST_DECODEDBranch instructions decodedBR_MISP_EXECSQ_FULL_STALL_CYCLESSuper Queue full stall cyclesBACLEARBranch address calculator clearsDTLB_MISSESData TLB missesMEM_INST_RETIREDMemory instructions retired (Precise Event)UOPS_ISSUEDL2_RQSTSTWO_UOP_INSTS_DECODEDTwo Uop instructions decodedLOAD_DISPATCHLoads dispatchedBACLEAR_FORCE_IQBACLEAR forced by Instruction queueSNOOPQ_REQUESTSSnoopq requestsOFFCORE_REQUESTSOffcore requestsLOAD_BLOCKLoads blockedMISALIGN_MEMORYMisaligned accessesINST_QUEUE_WRITE_CYCLESCycles instructions are written to the instruction queueLSD_OVERFLOWNumber of loops that cannot stream from the instruction queue.MACHINE_CLEARSMachine clear assertedFP_COMP_OPS_EXESSE/MMX micro-opsITLB_FLUSHITLB flushesBR_INST_RETIREDL1D_CACHE_PREFETCH_LOCK_FB_HITL1D prefetch load lock accepted in fill bufferLARGE_ITLBLarge ITLB accessesLSDLoop stream detectorL2_LINES_OUTITLB_MISSESL1D_PREFETCHL1D hardware prefetchSQ_MISCSuper Queue miscellaneousSEG_RENAME_STALLSSegment rename stall cyclesFP_ASSISTX87 Floating point assists (Precise Event)SIMD_INT_128128 bit SIMD operationsOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsMEM_STORE_RETIREDRetired storesINST_DECODEDMACRO_INSTS_FUSIONS_DECODEDCount the number of instructions decoded that are macros-fused but not necessarily executed or retiredMACRO_INSTSMacro-instructionsPARTIAL_ADDRESS_ALIASFalse dependencies due to partial address aliasingARITHCounts arithmetic multiply and divide operationsL2_TRANSACTIONSL2 transactionsINST_QUEUE_WRITESInstructions written to instruction queue.SB_DRAINStore bufferLOAD_HIT_PRELoad operations conflicting with software prefetchesMEM_UNCORE_RETIREDLoad instructions retired (Precise Event)L2_DATA_RQSTSBR_INST_EXECITLB_MISS_RETIREDRetired instructions that missed the ITLB (Precise Event)BPU_MISSED_CALL_RETBranch prediction unit missed call or returnSNOOPQ_REQUESTS_OUTSTANDINGOutstanding snoop requestsMEM_LOAD_RETIREDMemory loads retired (Precise Event)L1IL1I instruction fetchL2_WRITEL2 demand lock/store RFOSNOOP_RESPONSESnoopL1D cacheRESOURCE_STALLSRAT_STALLSCPU_CLK_UNHALTEDCycles when processor is not in halted stateL1D_WB_L2L1D writebacks to L2MISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareBR_MISP_RETIRED:ALL_BRANCHESTHREAD_ACTIVECycles thread is activeUOP_UNFUSIONCounts unfusion events due to floating point exception to a fused uopOFFCORE_RESPONSE_0Offcore response 0 (must provide at least one request and one response umasks)OFFCORE_RESPONSE_1Offcore response 1 (must provide at least one request and one response umasks)<???#.O?.O?.A?.A???R????O??l?????????c??.??? ???I? ?$????????? ?????R?????N?????`? ?????????L? ?& ? ? ??? ??' ??Q???<?(????" ?" ?Intel Westmere (single-socket)wsmIntel Westmere DPwsm_dpint^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;H Y { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  @ W W W W  #W$X%ret Wl#3W$3X%ret5Wl&IW$Ih Y  {'   Y 1 {' ;F ! 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gZvr$Y2gZvr$Y2Ycntmskpfm_intel_x86_cfgwsm_simd_int_128ufilterssize_tsizetypewsm_baclearwsm_br_inst_execvalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEwsm_simd_int_64_IO_save_endPFM_PMU_AMD64wsm_load_blockPFM_PMU_MIPS_SB1wsm_offcore_response_0_IO_write_basePFM_PMU_SPARC_NIAGARA2wsm_fp_comp_ops_exePFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainwsm_lsdPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFwsm_sq_miscwsm_inst_retiredPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEwsm_itlb_misseswsm_l2_data_rqstswsm_macro_instsnattrsPFM_PMU_TYPE_UNKNOWNwsm_l2_lines_outPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kwsm_large_itlb_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEintel_wsm_sp_supportos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlwsm_uops_executedintel_wsm_dp_supportwsm_br_misp_retiredPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000pfm_wsm_dp_detectcharmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64wsm_mem_uncore_retiredmodhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_twsm_cpu_clk_unhaltedPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encodingwsm_fp_assist_flags2_IO_read_baseget_event_nextwsm_l2_lines_inthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000wsm_load_dispatchwsm_snoopq_requests_outstandingpfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64wsm_uops_issuedPFM_PMU_I386_PMlong long intpfmlib_attr_desc_twsm_sb_drainunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endwsm_l2_transactionsPFM_PMU_INTEL_PPROumaskswsm_mem_store_retiredwsm_snoopq_requestsnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3pfm_wsm_init__pad1__pad2__pad3__pad4__pad5_sbufpfm_wsm_sp_detectis_precisewsm_dtlb_missesPFM_PMU_INTEL_SNBEP_UNC_UBOXwsm_ssex_uops_retiredPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CFwsm_ept_modewsm_br_misp_execpfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstrwsm_mem_inst_retiredpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMpfmlib_intel_wsm.cPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventswsm_l3_lat_cachenum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMwsm_l2_rqstssteppingcan_auto_encodeget_event_attr_infowsm_l1d_wb_l2wsm_machine_clearssizeintel_x86_modslong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12wsm_snoop_responsePFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3wsm_fp_mmx_transwsm_store_blocks_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_twsm_l2_writecodewsm_resource_stallswsm_uops_decodeddtypewsm_dtlb_load_missesget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Iosidwsm_misalign_memoryPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidwsm_cache_lock_cyclescodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBwsm_arithwsm_l1d_prefetchGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsarch_versionPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endpfm_intel_x86_config_twsm_ild_stallmodmskPFM_PMU_INTEL_X86_ARCHwsm_bpu_clearsPFM_PMU_AMD64_FAM10H_ISTANBUL_filenointel_wsm_pewsm_offcore_requestsreservedwsm_offcore_requests_outstandingPFM_PMU_INTEL_NHM_EXshort unsigned intwsm_mem_load_retireddfl_intvalidate_tablepmu_revwsm_inst_decoded_IO_write_ptrPFM_PMU_INTEL_SNB_EPwsm_l1dwsm_l1iPFM_DTYPE_FIXEDnum_cntrswsm_br_inst_retiredwsm_uops_retiredPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regwsm_rat_stallspfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx KAC F <PAC K \AC T .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @P"+ &"1; 6& UHC{)T`6g0bH0 {xvx 0>20p -  xH M P%4E@Y` Pa@s@@`!@" #`%0&) 7@-C.S@1h 3x 6`;@ =@?0AP`BP`CE HIP-J5LF OV@QgRs T@V0Y@ZP@[P[P^`cPgp,`mp>@r Ovo {~@p@@ K0KPB   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I.< IIW ITdr I  I@ I&  I I Ix&4 I>@OI IU\^ It I EO @K`/328 1386324440 1009 1009 100664 166776 ` ELF>@@UHH H}E}tE*t*tUHH H}E}tE*t-tUHH}]DP GQ COUNTThis event counts executed load operations FPU_DIV_ACTIVECycles that the divider is active, includes integer and floating pointFPU_DIVNumber of cycles the divider is activated, includes integer and floating pointFPU_DIV_ACTIVE:c=1:e=1NONTAKEN_CONDAll macro conditional non-taken branch instructionsTAKEN_CONDAll macro conditional taken branch instructionsNONTAKEN_DIRECT_JUMPAll macro unconditional non-taken branch instructions, excluding calls and indirectsTAKEN_DIRECT_JUMPAll macro unconditional taken branch instructions, excluding calls and indirectsNONTAKEN_INDIRECT_JUMP_NON_CALL_RETAll non-taken indirect branches that are not calls nor returnsTAKEN_INDIRECT_JUMP_NON_CALL_RETAll taken indirect branches that are not calls nor returnsTAKEN_RETURN_NEARAll taken indirect branches that have a return mnemonicTAKEN_DIRECT_NEAR_CALLAll taken non-indirect callsTAKEN_INDIRECT_NEAR_CALLAll taken indirect calls, including both register and memory indirectALL_BRANCHESAll near executed branches instructions (not necessarily retired)ALL_CONDITIONALAll macro conditional branch instructionsANY_CONDANY_INDIRECT_JUMP_NON_CALL_RETAll indirect branches that are not calls nor returnsANY_DIRECT_NEAR_CALLAll non-indirect callsABD All taken and not taken macro branches including far branches (Precise Event)CONDITIONALAll taken and not taken macro conditional branch instructions (Precise Event)FAR_BRANCHNumber of far branch instructions retired (Precise Event)NEAR_CALLAll macro direct and indirect near calls, does not count far calls (Precise Event)NEAR_RETURNNumber of near ret instructions retired (Precise Event)NEAR_TAKENNumber of near branch taken instructions retired (Precise Event)NOT_TAKENAll not taken macro branch instructions retired (Precise Event) @ All non-taken mispredicted macro conditional branch instructionsAll taken mispredicted macro conditional branch instructionsAll non-taken mispredicted indirect branches that are not calls nor returnsAll taken mispredicted indirect branches that are not calls nor returnsNONTAKEN_RETURN_NEARAll non-taken mispredicted indirect branches that have a return mnemonicAll taken mispredicted indirect branches that have a return mnemonicNONTAKEN_DIRECT_NEAR_CALLAll non-taken mispredicted non-indirect callsAll taken mispredicted non-indirect callsNONTAKEN_INDIRECT_NEAR_CALLAll nontaken mispredicted indirect calls, including both register and memory indirectAll taken mispredicted indirect calls, including both register and memory indirectAll mispredicted macro conditional branch instructionsANY_RETURN_NEARAll mispredicted indirect branches that have a return mnemonicAll mispredicted non-indirect callsAll mispredicted indirect branches that are not calls nor returnsAll mispredicted branch instructionsADHP` All mispredicted macro branches (Precise Event)All mispredicted macro conditional branch instructions (Precise Event)All macro direct and indirect near calls (Precise Event)Number of branch instructions retired that were mispredicted and not-taken (Precise Event)TAKENNumber of branch instructions retired that were mispredicted and taken (Precise Event)  SPLIT_LOCK_UC_LOCK_DURATIONCycles in which the L1D and L2 are locked, due to a UC lock or split lockCACHE_LOCK_DURATIONCycles in which the L1D is lockedRING0Unhalted core cycles the thread was in ring 0RING0_TRANSTransitions from rings 1, 2, or 3 to ring 0RING0:c=1:e=1RING123Unhalted core cycles the thread was in rings 1, 2, or 3REF_PCycles when the core is unhalted (count at 100 Mhz)THREAD_PCycles when thread is not halted Number of DSB to MITE switchesPENALTY_CYCLESCycles SB to MITE switches caused delay ALL_CANCELNumber of times a valid DSB fill has been cancelled for any reasonEXCEED_DSB_LINESDSB Fill encountered > 3 DSB linesOTHER_CANCELNumber of times a valid DSB fill has been cancelled not because of exceeding way limit MISS_CAUSES_A_WALKDemand load miss in all TLB levels which causes an page walk of any page sizeCAUSES_A_WALKSTLB_HITNumber of DTLB lookups for loads which missed first level DTLB but hit second level DTLB (STLB); No page walk.WALK_COMPLETEDDemand load miss in all TLB levels which causes a page walk that completes for any page sizeWALK_DURATIONCycles PMH is busy with a walkMiss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)First level miss but second level hit; no page walk. Only relevant if multiple levelsMiss in all TLB levels that causes a page walk that completes of any page size (4K/2M/4M/1G)Cycles PMH is busy with this walkANYCycles with any input/output SSE or FP assistsSIMD_INPUTNumber of SIMD FP assists due to input valuesSIMD_OUTPUTNumber of SIMD FP assists due to output valuesX87_INPUTNumber of X87 assists due to input valueX87_OUTPUTNumber of X87 assists due to output value X87Number of X87 uops executedSSE_FP_PACKED_DOUBLENumber of SSE double precision FP packed uops executedSSE_FP_SCALAR_SINGLENumber of SSE single precision FP scalar uops executedSSE_PACKED_SINGLENumber of SSE single precision FP packed uops executedSSE_SCALAR_DOUBLENumber of SSE double precision FP scalar uops executed @RECEIVEDNumber of hardware interrupts received by the processor L1D_MISSHardware prefetch requests that misses the L1D cache. A request is counted each time it accesses the cache and misses it, including if a block is applicable or if it hits the full buffer, for example. This accounts for both L1 streamer and IP-based Hw prefetchers MISSESNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses EMPTYCycles IDQ is emptyMITE_UOPSNumber of uops delivered to IDQ from MITE pathDSB_UOPSNumber of uops delivered to IDQ from DSB pathMS_DSB_UOPSNumber of uops delivered to IDQ when MS busy by DSBMS_MITE_UOPSNumber of uops delivered to IDQ when MS busy by MITEMS_UOPSNumber of uops were delivered to IDQ from MS by either DSB or MITEMITE_UOPS_CYCLESCycles where uops are delivered to IDQ from MITE (MITE active)MITE_UOPS:c=1DSB_UOPS_CYCLESCycles where uops are delivered to IDQ from DSB (DSB active)MS_DSB_UOPS_CYCLESCycles where uops delivered to IDQ when MS busy by DSBMS_DSB_UOPS:c=1MS_MITE_UOPS_CYCLESCycles where uops delivered to IDQ when MS busy by MITEMS_MITE_UOPS:c=1MS_UOPS_CYCLESCycles where uops delivered to IDQ from MS by either BSD or MITEMS_UOPS:c=1ALL_DSB_UOPSNumber of uops deliver from either DSB pathsALL_DSB_CYCLESCycles MITE/MS deliver anythingALL_MITE_UOPSNumber of uops delivered from either MITE pathsALL_MITE_CYCLESCycles DSB/MS deliver anythingANY_UOPSNumber of uops delivered to IDQ from any pathMS_DSB_UOPS_OCCUROccurences of DSB MS going activeMS_DSB_UOPS:c=1:e=1 0 0$$<CORENumber of non-delivered uops to RAT (use cmask to qualify further) LCPStall caused by changing prefix length of the instructionIQ_FULLStall cycles due to IQ fullINSTSNumber of instructions written to IQ every cycle ANY_PNumber of instructions retiredPREC_DISTPrecise instruction retired event to reduce effect of PEBS shadow IP distribution (Precise Event) RAT_STALL_CYCLESCycles RAT external stall is sent to IDQ for this threadRECOVERY_CYCLESCycles waiting to be recovered after Machine Clears due to all other cases except JEClearRECOVERY_STALLS_COUNTNumber of times need to wait after Machine Clears due to all other cases except JEClear@ITLB_FLUSHNumber of ITLB flushes, includes 4k/2M/4M pagesFLUSH ALLOCATED_IN_MNumber of allocations of L1D cache lines in modified (M) stateALL_M_REPLACEMENTNumber of cache lines in M-state evicted of L1D due to snoop HITM or dirty line replacementM_EVICTNumber of modified lines evicted from L1D due to replacementREPLACEMENTNumber of cache lines brought into the L1D cacheBANK_CONFLICTNumber of dispatched loads cancelled due to L1D bank conflicts with other load portsBANK_CONFLICT_CYCLESCycles with l1d blocks due to bank conflicts OCCURRENCESOccurrences of L1D_PEND_MISS going activePENDING:e=1:c=1EDGEPENDINGNumber of L1D load misses outstanding every cyclePENDING_CYCLESCycles with L1D load misses outstandingPENDING:c=1HIT_ENon rejected writebacks from L1D to L2 cache lines in E stateHIT_MNon rejected writebacks from L1D to L2 cache lines in M stateL2 cache lines filling (counting does not cover rejects)EL2 cache lines in E state (counting does not cover rejects)IL2 cache lines in I state (counting does not cover rejects)SL2 cache lines in S state (counting does not cover rejects)DEMAND_CLEANL2 clean line evicted by a demandDEMAND_DIRTYL2 dirty line evicted by a demandPREFETCH_CLEANL2 clean line evicted by a prefetchPREFETCH_DIRTYL2 dirty line evicted by an MLC PrefetchDIRTY_ANYAny L2 dirty line evicted (does not cover rejects) ALL_CODE_RDAny ifetch request to L2 cacheCODE_RD_HITL2 cache hits when fetching instructionsCODE_RD_MISSL2 cache misses when fetching instructionsALL_DEMAND_DATA_RDDemand data read requests to L2 cacheALL_DEMAND_RD_HITDemand data read requests that hit L2ALL_PFAny L2 HW prefetch request to L2 cachePF_HITRequests from the L2 hardware prefetchers that hit L2 cachePF_MISSRequests from the L2 hardware prefetchers that miss L2 cacheRFO_ANYAny RFO requests to L2 cacheRFO_HITSRFO requests that hit L2 cacheRFO_MISSRFO requests that miss L2 cache0 @ RFOs that hit cache lines in E stateMISSRFOs that miss cache (I state)RFOs that hit cache lines in M stateALLRFOs that access cache lines in any state Transactions accessing MLC pipeCODE_RDL2 cache accesses when fetching instructionsL1D_WBL1D writebacks that access L2 cacheLOADDemand Data Read* requests that access L2 cacheL2_FILLL2 fill requests that access L2 cacheL2_WBL2 writebacks that access L2 cacheALL_PREFETCHL2 or L3 HW prefetches that access L2 cache (including rejects)RFORFO requests that access L2 cache @DATA_UNKNOWNBlocked loads due to store buffer blocks with unknown dataSTORE_FORWARDLoads blocked by overlapping with store buffer that cannot be forwardedNO_SRNumber of split loads blocked due to resource not availableALL_BLOCKNumber of cases where any load is blocked but has not DCU missADDRESS_ALIASFalse dependencies in MOB due to partial compare on addressALL_STA_BLOCKNumber of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this typeHW_PFNon sw-prefetch load dispatches that hit the fill buffer allocated for HW prefetchSW_PFNon sw-prefetch load dispatches that hit the fill buffer allocated for SW prefetchCore-originated cacheable demand requests missed L3REFERENCECore-originated cacheable demand requests that refer to L3MASKMOVThe number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0MEMORY_ORDERINGNumber of Memory Ordering Machine Clears detectedSMCSelf-Modifying Code detected XSNP_HITLoad LLC Hit and a cross-core Snoop hits in on-pkg core cache (Precise Event)XSNP_HITMLoad had HitM Response from a core on same socket (shared LLC) (Precise Event)XSNP_MISSLoad LLC Hit and a cross-core Snoop missed in on-pkg core cache (Precise Event)XSNP_NONELoad hit in last-level (L3) cache with no snoop needed (Precise Event)LLC_MISSCounts load driven L3 misses and some non simd split loads (Precise Event) HIT_LFBA load missed L1D but hit the Fill Buffer (Precise Event)L1_HITLoad hit in nearest-level (L1D) cache (Precise Event)L2_HITLoad hit in mid-level (L2) cache (Precise Event)L3_HITL3_MISSRetired load uops which data sources were data missed LLC (excluding unknown data source)@ LATENCY_ABOVE_THRESHOLDMemory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)PRECISE_STORECapture where stores occur, must use with PEBS (Precise Event required)ALL_LOADSAny retired loads (Precise Event)ANY_LOADSALL_STORESAny retired stores (Precise Event)ANY_STORESLOCK_LOADSLocked retired loads (Precise Event)LOCK_STORESLocked retired stores (Precise Event)SPLIT_LOADSRetired loads causing cacheline splits (Precise Event)SPLIT_STORESRetired stores causing cacheline splits (Precise Event)STLB_MISS_LOADSSTLB misses dues to retired loads (Precise Event)STLB_MISS_STORESSTLB misses dues to retired stores (Precise Event)!"ABLOADSSpeculative cache-line split load uops dispatched to the L1DSTORESSpeculative cache-line split Store-address uops dispatched to L1DALL_DATA_RDDemand and prefetch read requests sent to uncoreALL_DATA_READDEMAND_CODE_RDOffcore code read requests, including cacheable and un-cacheablesDEMAND_DATA_RDDemand Data Read requests sent to uncoreDEMAND_RFOOffcore Demand RFOs, includes regular RFO, Locks, ItoMSQ_FULLOffcore requests buffer cannot take more entries for this thread core ALL_DATA_RD_CYCLESCycles with cacheable data read transactions in the superQALL_DATA_RD:c=1DEMAND_CODE_RD_CYCLESCycles with demand code reads transactions in the superQDEMAND_CODE_RD:c=1DEMAND_DATA_RD_CYCLESCycles with demand data read transactions in the superQDEMAND_DATA_RD:c=1Cacheable data read transactions in the superQ every cycleCode read transactions in the superQ every cycleDemand data read transactions in the superQ every cycleOutstanding RFO (store) transactions in the superQ every cycleDEMAND_RFO_CYCLESCycles with outstanding RFO (store) transactions in the superQDEMAND_RFO:c=1ITLB_MISS_RETIREDNumber of instructions that experienced an ITLB missAVX_TO_SSENumber of transitions from AVX-256 to legacy SSE when penalty applicableSSE_TO_AVXNumber of transitions from legacy SSE to AVX-256 when penalty applicable FLAGS_MERGE_UOPNumber of flags-merge uops in flight in each cycleCYCLES_FLAGS_MERGE_UOPCycles in which flags-merge uops in flightFLAGS_MERGE_UOP:c=1MUL_SINGLE_UOPNumber of Multiply packed/scalar single precision uops allocatedSLOW_LEA_WINDOWNumber of cycles with at least one slow LEA uop allocated  @Cycles stalled due to Resource Related reasonLBCycles stalled due to lack of load buffersRSCycles stalled due to no eligible RS entry availableSBCycles stalled due to no store buffers available (not including draining from sync)ROBCycles stalled due to re-order buffer fullFCSWCycles stalled due to writing the FPU control wordMXCSRCycles stalled due to the MXCSR register ranme occurring too close to a previous MXCSR renameMEM_RSCycles stalled due to LB, SB or RS being completely in useLB:SB:RS  @ALL_FL_EMPTYCycles stalled due to free list emptyALL_PRF_CONTROLCycles stalls due to control structures full for physical registersANY_PRF_CONTROLBOB_FULLCycles Allocator is stalled due Branch Order BufferOOO_RSRCCycles stalled due to out of order resources full @OLBR_INSERTSCount each time an new LBR record is saved by HW EMPTY_CYCLESCycles the RS is empty for this thread PACKED_SINGLECounts 256-bit packed single-precisionPACKED_DOUBLECounts 256-bit packed double-precisionSPLIT_LOCKSplit locks in SQ DTLB_THREADNumber of DTLB flushes of thread-specific entriesSTLB_ANYNumber of STLB flushes Counts total number of uops dispatched from any threadSTALL_CYCLESCounts number of cycles no uops were dispatched on this threadTHREAD:c=1:i=1THREADCounts total number of uops to be dispatched per-thread each cyclePORT_0Cycles which a Uop is dispatched on port 0PORT_1Cycles which a Uop is dispatched on port 1PORT_2_LDCycles in which a load uop is dispatched on port 2PORT_2_STACycles in which a store uop is dispatched on port 2PORT_2Cycles in which a uop is dispatched on port 2PORT_3_LDCycles in which a load uop is disptached on port 3PORT_3_STACycles in which a store uop is disptached on port 3PORT_3Cycles in which a uop is disptached on port 3PORT_4Cycles which a uop is dispatched on port 4PORT_5Cycles which a Uop is dispatched on port 5  0@Number of uops issued by the RAT to the Reservation Station (RS)CORE_STALL_CYCLESCycles no uops issued on this core (by any thread)ANY:c=1:i=1:t=1Cycles no uops issued by this threadANY:c=1:i=1 All uops that actually retired (Precise Event)RETIRE_SLOTSNumber of retirement slots used (Precise Event)Cycles no executable uop retired (Precise Event)ALL:c=1:i=1TOTAL_CYCLESTotal cycles using precise uop retired event (Precise Event)ALL:c=16 DMND_DATA_RDRequest: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesDMND_IFETCHRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesWBRequest: number of writebacks (modified to exclusive) transactionsPF_DATA_RDRequest: number of data cacheline reads generated by L2 prefetchersPF_RFORequest: number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: number of code reads generated by L2 prefetchersPF_LLC_DATA_RDRequest: number of L3 prefetcher requests to L2 for loadsPF_LLC_RFORequest: number of RFO requests generated by L2 prefetcherPF_LLC_IFETCHRequest: number of L2 prefetcher requests to L3 for instruction fetchesBUS_LOCKSRequest: number bus lock and split lock requestsSTRM_STRequest: number of streaming store requestsOTHERRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCH | PF_LLC_IFETCHPF_IFETCH:DMND_IFETCH:PF_LLC_IFETCHANY_REQUESTRequest: combination of all request umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHERANY_DATARequest: combination of DMND_DATA | PF_DATA_RD | PF_LLC_DATA_RDDMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RDANY_RFORequest: combination of DMND_RFO | PF_RFO | PF_LLC_RFODMND_RFO:PF_RFO:PF_LLC_RFOANY_RESPONSEResponse: count any response typeNO_SUPPSupplier: counts number of times supplier information is not availableLLC_HITMSupplier: counts L3 hits in M-state (initial lookup)LLC_HITESupplier: counts L3 hits in E-stateLLC_HITSSupplier: counts L3 hits in S-stateLLC_HITFSupplier: counts L3 hits in F-stateLLC_MISS_LOCAL_DRAMSupplier: counts L3 misses to local DRAMMISS_DRAMLLC_MISS_LOCALLLC_HITMESFSupplier: counts L3 hits in any state (M, E, S, F)LLC_HITM:LLC_HITE:LLC_HITS:LLC_HITFSNP_NONESnoop: counts number of times no snoop-related information is availableSNP_NOT_NEEDEDSnoop: counts the number of times no snoop was needed to satisfy the requestNO_SNP_NEEDEDSNP_MISSSnoop: counts number of times a snoop was needed and it missed all snooped cachesSNP_NO_FWDSnoop: counts number of times a snoop was needed and it hit in at leas one snooped cacheSNP_FWDSnoop: counts number of times a snoop was needed and data was forwarded from a remote socketHITMSnoop: counts number of times a snoop was needed and it hitM-ed in local or remote cacheNON_DRAMSnoop: counts number of times target was a non-DRAM system address. This includes MMIO transactionsSNP_ANYSnoop: any snoop reasonSNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAM @D "I @@@< ?Counts the number of times the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end CYCLES_L2_PENDINGCycles with pending L2 miss loadsCYCLES_L1D_PENDINGCycles with pending L1D load cache missesCYCLES_NO_DISPATCHCycles of dispatch stallsSTALLS_L2_PENDINGExecution stalls due to L2 pending loadsSTALLS_L1D_PENDINGExecution stalls due to L1D pending loadsAGU_BYPASS_CANCELNumber of executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another pageARITHCounts arithmetic multiply operationsBACLEARSBranch resteeredBR_INST_EXECBranch instructions executedBR_INST_RETIREDRetired branch instructionsBR_MISP_EXECMispredicted branches executedBR_MISP_RETIREDMispredicted retired branchesBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionBR_INST_RETIRED:ALL_BRANCHESMISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareBR_MISP_RETIRED:ALL_BRANCHESLOCK_CYCLESLocked cycles in L1D and L2CPL_CYCLESUnhalted core cycles at a specific ring levelCPU_CLK_UNHALTEDCycles when processor is not in halted stateDSB2MITE_SWITCHESDSB_FILLDSB fillsDTLB_LOAD_MISSESData TLB load missesDTLB_STORE_MISSESData TLB store missesFP_ASSISTX87 Floating point assistsFP_COMP_OPS_EXECounts number of floating point eventsHW_INTERRUPTSHW_PRE_REQHardware prefetch requestsICACHEInstruction Cache accessesIDQIDQ operationsIDQ_UOPS_NOT_DELIVEREDUops not deliveredILD_STALLInstruction Length Decoder stallsINSTS_WRITTEN_TO_IQInstructions written to IQINST_RETIREDInstructions retiredINSTRUCTION_RETIREDNumber of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDINT_MISCMiscellaneous internalsITLBInstruction TLBITLB_MISSESInstruction TLB missesL1DL1D cacheL1D_BLOCKSL1D is blockingL1D_PEND_MISSL1D pending missesL2_L1D_WB_RQSTSWriteback requests from L1D to L2L2_LINES_INL2 lines alloacatedL2_LINES_OUTL2 lines evictedL2_RQSTSL2 requestsL2_STORE_LOCK_RQSTSL2 store lock requestsL2_TRANSL2 transactionsLAST_LEVEL_CACHE_MISSESThis is an alias for L3_LAT_CACHE:MISSL3_LAT_CACHE:MISSLLC_MISSESAlias for LAST_LEVEL_CACHE_MISSESLAST_LEVEL_CACHE_REFERENCESThis is an alias for L3_LAT_CACHE:REFERENCEL3_LAT_CACHE:REFERENCELLC_REFERENCESAlias for LAST_LEVEL_CACHE_REFERENCESLD_BLOCKSBlocking loadsLD_BLOCKS_PARTIALPartial load blocksLOAD_HIT_PRELoad dispatches that hit fill bufferL3_LAT_CACHECore-originated cacheable demand requests to L3MACHINE_CLEARSMachine clear assertedMEM_LOAD_UOPS_LLC_HIT_RETIREDL3 hit loads uops retiredMEM_LOAD_LLC_HIT_RETIREDL3 hit loads uops retired (deprecated use MEM_LOAD_UOPS_LLC_HIT_RETIRED)MEM_LOAD_UOPS_MISC_RETIREDLoads and some non simd split loads uops retiredMEM_LOAD_MISC_RETIREDLoads and some non simd split loads uops retired (deprecated use MEM_LOAD_UOPS_MISC_RETIRED)MEM_LOAD_UOPS_RETIREDMemory loads uops retiredMEM_LOAD_RETIREDMemory loads uops retired (deprecated use MEM_LOAD_UOPS_RETIRED)MEM_TRANS_RETIREDMemory transactions retiredMEM_UOPS_RETIREDMemory uops retiredMEM_UOP_RETIREDMemory uops retired (deprecated use MEM_UOPS_RETIRED)MISALIGN_MEM_REFMisaligned memory referencesOFFCORE_REQUESTSOffcore requestsOFFCORE_REQUESTS_BUFFEROffcore requests bufferOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsOTHER_ASSISTSCount hardware assistsPARTIAL_RAT_STALLSPartial Register Allocation Table stallsRESOURCE_STALLSResource related stall cyclesRESOURCE_STALLS2ROB_MISC_EVENTSReorder buffer eventsRS_EVENTSReservation station eventsSIMD_FP_256Counts 256-bit packed floating point instructionsSQ_MISCSuperQ eventsTLB_FLUSHTLB flushesUNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)UNHALTED_REFERENCE_CYCLESUnhalted reference cyclesUOPS_DISPATCHEDUops dispatchedUOPS_DISPATCHED_PORTUops dispatch to specific portsUOPS_ISSUEDUops issuedUOPS_RETIREDUops retiredCYCLE_ACTIVITYStalled cyclesOFFCORE_RESPONSE_0Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)OFFCORE_RESPONSE_1?????????c?\?<????I????N??y??????? ???Q??H?(???$ ?'??.A?.A?.O?.O???L?.???????? ? ????`??Y??[??^????<?#? ???/$ ?$ ? ABD  @ ADHP`        @    0 0$$<  @   0 @   @ LOCAL_DRAMLoad uops that miss in the L3 and hit local DRAMREMOTE_DRAMLoad uops that miss in the L3 and hit remote DRAM @ Memory load instructions retired above programmed clocks, minimum value threshold is 4 (Precise Event required)!"AB    @  @ @O      0@  LLC_MISS_REMOTESupplier: counts L3 misses to remote DRAMLLC_MISS_REMOTE_DRAM @D "I @@< ? Load uops retired which hit the L3 cacheMEM_LOAD_UOPS_LLC_MISS_RETIREDLoad uops retired which miss the L3 cache?????????c?\?<????I????N??y??????? ???Q??H?(???$ ?'??.A?.A?.O?.O???L?.????????? ? ????`??Y??[??^????<?#? ???/$ ?$ ?Intel Sandy BridgesnbIntel Sandy Bridge EPsnb_epint^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;H Y { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  @ W W W W  #W$X%ret!Wl#4W$4X%ret6Wl&IW$Ih Y  {'   Y 1 {' &F ! Y [ { ' 4p K Y  {'  u Y  {'   Y  {'  (   ! Y  {( 4 ( /O !( <j !( I ( [ ( x (  (  (   ( ' ( B  Y W {( m G( E ( M !( Z ( b !( p (  ! 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unsigned intsnb_uops_dispatched_portmax_encodingsnbep_ild_stallsnbep_l2_lines_in_flags2snb_l2_transsnb_dsb_fill_IO_read_basesnb_partial_rat_stallsget_event_nextsnb_offcore_requeststhissnb_resource_stalls_unused2snb_resource_stalls2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTsnb_itlbudescintel_snb_ep_supportPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000snb_agu_bypass_cancelpfm_dtype_tPFM_ATTR_UMASKsnb_hw_interrupts_old_offsetucodePFM_PMU_INTEL_IVB_EPsnbep_idqPFM_PMU_I386_P6snbep_ld_blocks_partialPFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamesnb_uops_retiredPFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1snb_fp_assistsnb_mem_load_uops_retiredintel_x86_umask_tsnbep_ld_blockspfmlib_intel_snb.csnbep_rob_misc_eventsPFM_PMU_INTEL_PPROumasksnpattrscountdfl_booleventsnb_tlb_flush_IO_buf_basesnbep_other_assistsunsigned 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intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidsnb_l2_store_lock_rqstscodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitssnb_l1d_blocksarch_versionsnbep_mem_trans_retiredsnb_hw_pre_reqPFM_PMU_INTEL_SNBEP_UNC_PCUsnbep_fp_comp_ops_exe_IO_write_endPFM_OS_MAXsnbep_l2_trans_IO_read_endpfm_intel_x86_config_tmodmsksnb_l1d_pend_missPFM_PMU_INTEL_X86_ARCHsnbep_machine_clearsPFM_PMU_AMD64_FAM10H_ISTANBULsnbep_mem_uops_retiredintel_snb_pe_filenosnb_load_hit_presnb_br_misp_retiredsnbep_uops_retiredreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intsnbep_offcore_requests_buffervalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPsnbep_fp_assistPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTsnbep_l1d_pend_missPFM_PMU_MIPS_74Kdisplay_regsnbep_dtlb_store_missespfm_os_tsnb_ld_blocks_partialsupported_plmsnbep_insts_written_to_iqpfmlib_event_desc_tsnbep_l2_rqstssnbep_misalign_mem_refsnbep_mem_load_uops_llc_hit_retiredGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx KAC F <KAC F \AC T .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @0+ &ح1;I 6hHLCS6Tj6gl0b0 {lv 0n%0-يx0HXؑ` 8 @P*`4@`E 0Y@j~@@!#&@)@," .P4/PC`0PN`5PV;Pq;<P=?@B@D@F@ HI@  L Pp)@T@A WNZ@\@]r^_`ac@`ePf`i l -oBqWsPsvz@|@@ PP@P$2F _o @  P``P``0"8`J[r@@ P PP P*@PGW@Pq@@@ @@p@1@@@Ph{@ @ ` P  )A` Xo P @ `! P7 `PG Y `Pg w `  `!  $ % `'@ 2P 3  5@ K& KK8    E Z l ~      ! ? a |    pfmlib_intel_snb.csnb_agu_bypass_cancelsnb_arithsnb_br_inst_execsnb_br_inst_retiredsnb_br_misp_execsnb_br_misp_retiredsnb_lock_cyclessnb_cpl_cyclessnb_cpu_clk_unhaltedsnb_dsb2mite_switchessnb_dsb_fillsnb_dtlb_load_missessnb_dtlb_store_missessnb_fp_assistsnb_fp_comp_ops_exesnb_hw_interruptssnb_hw_pre_reqsnb_icachesnb_idqsnb_idq_uops_not_deliveredsnb_ild_stallsnb_insts_written_to_iqsnb_inst_retiredsnb_int_miscsnb_itlbsnb_l1dsnb_l1d_blockssnb_l1d_pend_misssnb_l2_l1d_wb_rqstssnb_l2_lines_insnb_l2_lines_outsnb_l2_rqstssnb_l2_store_lock_rqstssnb_l2_transsnb_ld_blockssnb_ld_blocks_partialsnb_load_hit_presnb_l3_lat_cachesnb_machine_clearssnb_mem_load_uops_llc_hit_retiredsnb_mem_load_uops_misc_retiredsnb_mem_load_uops_retiredsnb_mem_trans_retiredsnb_mem_uops_retiredsnb_misalign_mem_refsnb_offcore_requestssnb_offcore_requests_buffersnb_offcore_requests_outstandingsnb_other_assistssnb_partial_rat_stallssnb_resource_stallssnb_resource_stalls2snb_rob_misc_eventssnb_rs_eventssnb_simd_fp_256snb_sq_miscsnb_tlb_flushsnb_uops_dispatchedsnb_uops_dispatched_portsnb_uops_issuedsnb_uops_retiredsnb_offcore_responsesnb_baclearssnb_cycle_activityintel_snb_pesnbep_agu_bypass_cancelsnbep_arithsnbep_br_inst_execsnbep_br_inst_retiredsnbep_br_misp_execsnbep_br_misp_retiredsnbep_lock_cyclessnbep_cpl_cyclessnbep_cpu_clk_unhaltedsnbep_dsb2mite_switchessnbep_dsb_fillsnbep_dtlb_load_missessnbep_dtlb_store_missessnbep_fp_assistsnbep_fp_comp_ops_exesnbep_hw_interruptssnbep_hw_pre_reqsnbep_icachesnbep_idqsnbep_idq_uops_not_deliveredsnbep_ild_stallsnbep_insts_written_to_iqsnbep_inst_retiredsnbep_int_miscsnbep_itlbsnbep_l1dsnbep_l1d_blockssnbep_l1d_pend_misssnbep_l2_l1d_wb_rqstssnbep_l2_lines_insnbep_l2_lines_outsnbep_l2_rqstssnbep_l2_store_lock_rqstssnbep_l2_transsnbep_ld_blockssnbep_ld_blocks_partialsnbep_load_hit_presnbep_l3_lat_cachesnbep_machine_clearssnbep_mem_load_uops_llc_hit_retiredsnbep_mem_load_uops_llc_miss_retiredsnbep_mem_load_uops_misc_retiredsnbep_mem_load_uops_retiredsnbep_mem_trans_retiredsnbep_mem_uops_retiredsnbep_misalign_mem_refsnbep_offcore_requestssnbep_offcore_requests_buffersnbep_offcore_requests_outstandingsnbep_other_assistssnbep_partial_rat_stallssnbep_resource_stallssnbep_resource_stalls2snbep_rob_misc_eventssnbep_rs_eventssnbep_simd_fp_256snbep_sq_miscsnbep_tlb_flushsnbep_uops_dispatchedsnbep_uops_dispatched_portsnbep_uops_issuedsnbep_uops_retiredsnbep_offcore_responsesnbep_baclearssnbep_cycle_activityintel_snbep_pepfm_snb_detectpfm_snb_ep_detectpfm_snb_initpfm_intel_x86_detectpfm_intel_x86_cfgintel_snb_supportintel_x86_modspfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_can_auto_encodepfm_intel_x86_get_event_attr_infopfm_intel_x86_get_encodingpfm_intel_x86_get_perf_encodingpfm_intel_x86_perf_validate_pattrspfm_intel_x86_validate_tableintel_snb_ep_support !3Xl~`IsI@`HPXhpxwII@ 5HPKXhpx@H`h?@HDP08X #(8ppx  ` Zh p  p Z  P X    0  8  N `    ( p@ xP   @HDXX080H# (ppx(Rp`h WhPX    (hp x0z@`Hh08lx@_p@!@ H!P ! ! ! ! #0"#H"$"$H" $0"`$"h$"$#$0#%#%#&0"&P%&"&P%&0" '"('%p'#x'%'#'X&@)(H)()G()X()()(0*(8*(*)*)@,*H,*,*,+,?+,X+0-+8-+-+-+ .-(.-/p./.`0/h0/`50h5050506161P6>1X6P161616161@72H702P7o27}27272727308'388@3@8x38383838383 9%4(984p9X4x9h49494:4:4`:4h:5p:25;:;:;P;;X;<;<;<`<<h<=<=<===(=?@>?X>?>?> @?(@?@p@@@A@A@ Ap@B`ABpACACA`C$BhC0BCmBCBDDDDEeDED@F`EHFpEPFEFEFpEF`EFEFE0GE8GF@G(F HG(HGpHGxHGI(IHJHJI`JOo l(}Xq`hs۽vz (0X@|`Yhii@ (ȾX`h"*@8B N(h`ǿh 0 P(\X`hhu 7(X `h ?`hDPPXX@#H8p08ZppZ (px   `N h`     P@ XP   PDXXX@0HH#0p8(Rp ( pWxh`h  ` hh `h0z`hPX`08PlXx@_p@@ HP     @0"HH""H"0"""0#80###0"P%0"8P%@0""%#% #(X&((G(X( (((p(x()) *(*p*x+?+X+++`+h+-- p.(.//00008011>1P1 1(1p1x1202o2}22`2h2p3'3@3x3333P3X3%484X4h4@4H4444525@:H:P;X;;;@`<Hh<<<=(=@@>HX>>>??@p@H@@@p@`ApA0A8A$B0BmBB D(DpeDxD`EpEEEpE `E`EhEEF(FGGPGXG(HHI@ >B(>OX>`>`h>i>>u>>>>?@ ?(?ظ0?`?h? p??B?`????B @޹(@X@`@h@ @@@0@@U@hA@ A(AXA`AhA4A AA4AA A4A4B  BY(BxXB` `BhBpBYB` BB3B BMB`BC  C(CXC`CϼhCC`CCCϼC`C>COD Dl(D}XD `DhDDDD۽D DDE E(E0XE`EYhEiEEEiE`EEF F(FȾXF``FhFFF"F*F`F8FBG GN(Gh`GǿhGGG G` GG0H`! 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@K`/348 1386324440 1009 1009 100664 31552 ` ELF>@@@UHH H}E}tE*t*tLMNOMISSNumber of snoop missesINVALNumber of snoop invalidates of a non-modified lineHITNumber of snoop hits of a non-modified lineHITMNumber of snoop hits of a modified lineINVAL_MNumber of snoop invalidates of a modified lineANY_SNPNumber of snoopsEXTERNAL_FILTERFilter on cross-core snoops initiated by this Cbox due to external snoop requestXCORE_FILTERFilter on cross-core snoops initiated by this Cbox due to processor core memory requestEVICTION_FILTERFilter on cross-core snoops initiated by this Cbox due to LLC eviction @ STATE_MNumber of LLC lookup requests for a line in modified stateSTATE_ENumber of LLC lookup requests for a line in exclusive stateSTATE_SNumber of LLC lookup requests for a line in shared stateSTATE_INumber of LLC lookup requests for a line in invalid stateSTATE_MESINumber of LLC lookup requests for a lineREAD_FILTERFilter on processor core initiated cacheable read requestsWRITE_FILTERFilter on processor core initiated cacheable write requestsEXTSNP_FILTERFilter on external snoop requestsANY_FILTERFilter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests  @ ALLCounts cycles weighted by the number of requests waiting for data returning from the memory controller, (includes coherent and non-coherent requests initiated by cores, processor graphic units, or LLC) Counts number of coherent and in-coherent requests initiated by cores, processor graphic units, or LLCWRITESCounts the number of allocated write entries, include full, partial, and LLC evictionsEVICTIONSCounts the number of LLC evictions allocated Cycles weighted by number of requests pending in Coherency Tracker Number of requests allocated in Coherency Tracker UNC_CLOCKTICKSuncore clock ticksUNC_CBO_XSNP_RESPONSESnoop responsesUNC_CBO_CACHE_LOOKUPLLC cache lookups" 4 Snoop responses (must provide a snoop type and filter)" 4 UNC_ARB_TRK_OCCUPANCYARB tracker occupancyUNC_ARB_COH_TRK_OCCUPANCYCoherency traffic occupancyUNC_ARB_COH_TRK_REQUESTCoherency traffic requestsIntel Sandy Bridge C-box0 uncoresnb_unc_cbo0uncore_cbox_0Intel Sandy Bridge C-box1 uncoresnb_unc_cbo1uncore_cbox_1Intel Sandy Bridge C-box2 uncoresnb_unc_cbo2uncore_cbox_2Intel Sandy Bridge C-box3 uncoresnb_unc_cbo3uncore_cbox_3:int^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;H Y { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  @ W W W W  #"W$"X%ret$Wl Y  {&  & P  Y  {&   Y  {&  & 6 & P  e {& z U  {& Τ &  U'S 'T 'U 'V ( @ -)( 8"% $ > $ > : ; I  I : ; : ;I8 : ;  : ;  : ; I8 I !I/ &I'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8  : ; !&"'#.: ; 'I@B$: ; I%4: ; I&4: ; I'4: ; I?(4: ; I?<)!,KmJ /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_intel_snb_unc.ctypes.hstddef.hstdint.hstdio.hlibio.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hintel_snb_unc_events.h "gZvr$Ycntmskpfm_intel_x86_cfgufilterssnb_unc_cbo_xsnp_responsesize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intpfm_snb_unc_detectPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kintel_x86_mods_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charintel_snb_unc_cbo1_supportPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlPFM_PMU_MIPS_R10000intel_snb_unc_cbo0_pePFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000charmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tintel_snb_unc_cbo0_supportmodmsk_reqdfl_val64intel_snb_unc_cbo_pemodhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIsnb_unc_arb_coh_trk_requestuflagslong unsigned intmax_encoding_flags2_IO_read_baseget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endintel_snb_unc_arb_pePFM_PMU_INTEL_PPROumasksnpattrscountdfl_booleventintel_snb_unc_cbo2_support_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CFsnb_unc_arb_trk_occupancy_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEsnb_unc_arb_coh_trk_occupancyPFM_PMU_INTEL_ATOMintel_snb_unc_cbo3_supportsteppingcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3snb_unc_cbo_cache_lookup_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsarch_versionPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endpfm_intel_x86_config_tmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24Ksnb_unc_arb_trkPFM_OS_PERF_EVENT_EXTpfmlib_intel_snb_unc.cPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx KAC F .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @KLH+ &M1;< 6TH>C0[T( g'*0bz0 {W*qv{ 0+'0>-? ?8({X?E I@2K` Pe uPP``K   )DSq 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W /372 1386324440 1009 1009 100664 101152 ` ELF>@@UHH H}E}tE*t:tUHH H}E}tE*t>tUHH}]JJ gJ FPU_DIV_ACTIVECycles that the divider is active, includes integer and floating pointFPU_DIVNumber of cycles the divider is activated, includes integer and floating pointFPU_DIV_ACTIVE:c=1:e=1NONTAKEN_CONDAll macro conditional non-taken branch instructionsTAKEN_CONDAll macro conditional taken branch instructionsTAKEN_DIRECT_JUMPAll macro unconditional taken branch instructions, excluding calls and indirectsNONTAKEN_INDIRECT_JUMP_NON_CALL_RETAll non-taken indirect branches that are not calls nor returnsTAKEN_INDIRECT_JUMP_NON_CALL_RETAll taken indirect branches that are not calls nor returnsTAKEN_NEAR_RETURNAll taken indirect branches that have a return mnemonicTAKEN_DIRECT_NEAR_CALLAll taken non-indirect callsTAKEN_INDIRECT_NEAR_CALLAll taken indirect calls, including both register and memory indirectALL_BRANCHESAll near executed branches instructions (not necessarily retired)ALL_CONDAll macro conditional branch instructionsANY_CONDANY_INDIRECT_JUMP_NON_CALL_RETAll indirect branches that are not calls nor returnsANY_DIRECT_NEAR_CALLAll non-indirect callsAD All taken and not taken macro branches including far branches (Precise Event)CONDAll taken and not taken macro conditional branch instructions (Precise Event)FAR_BRANCHNumber of far branch instructions retired (Precise Event)NEAR_CALLAll macro direct and indirect near calls, does not count far calls (Precise Event)NEAR_RETURNNumber of near ret instructions retired (Precise Event)NEAR_TAKENNumber of near branch taken instructions retired (Precise Event)NOT_TAKENAll not taken macro branch instructions retired (Precise Event) @ All non-taken mispredicted macro conditional branch instructionsAll taken mispredicted macro conditional branch instructionsAll taken mispredicted indirect branches that are not calls nor returnsAll taken mispredicted indirect branches that have a return mnemonicAll taken mispredicted non-indirect callsAll taken mispredicted indirect calls, including both register and memory indirectAll mispredicted macro conditional branch instructionsANY_RETURN_NEARAll mispredicted indirect branches that have a return mnemonicAll mispredicted non-indirect callsAll mispredicted indirect branches that are not calls nor returnsAll mispredicted branch instructionsA All mispredicted macro branches (Precise Event)All mispredicted macro conditional branch instructions (Precise Event)CONDITIONALNumber of branch instructions retired that were mispredicted and taken (Precise Event)  SPLIT_LOCK_UC_LOCK_DURATIONCycles in which the L1D and L2 are locked, due to a UC lock or split lockCACHE_LOCK_DURATIONCycles in which the L1D is lockedRING0Unhalted core cycles the thread was in ring 0RING0_TRANSTransitions from rings 1, 2, or 3 to ring 0RING0:c=1:e=1RING123Unhalted core cycles the thread was in rings 1, 2, or 3REF_PCycles when the core is unhalted (count at 100 Mhz)REF_XCLKTHREAD_PCycles when thread is not halted COUNTNumber of DSB to MITE switches EXCEED_DSB_LINESDSB Fill encountered > 3 DSB lines MISS_CAUSES_A_WALKDemand load miss in all TLB levels which causes a page walk of any page sizeWALK_COMPLETEDDemand load miss in all TLB levels which causes a page walk that completes for any page sizeWALK_DURATIONCycles PMH is busy with a walk due to demand loadsDEMAND_LD_MISS_CAUSES_A_WALKDEMAND_LD_WALK_COMPLETEDDEMAND_LD_WALK_DURATIONSTLB_HITNumber of load operations that missed L1TLB but hit L2TLBLARGE_WALK_COMPLETEDNumber of large page walks completed for demand loads_Miss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)CAUSES_A_WALKFirst level miss but second level hit; no page walk. Only relevant if multiple levelsMiss in all TLB levels that causes a page walk that completes of any page size (4K/2M/4M/1G)Cycles PMH is busy with this walkANYCycles with any input/output SSE or FP assistsSIMD_INPUTNumber of SIMD FP assists due to input valuesSIMD_OUTPUTNumber of SIMD FP assists due to output valuesX87_INPUTNumber of X87 assists due to input valueX87_OUTPUTNumber of X87 assists due to output value MISSESNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accessesIFETCH_STALLNumber of cycles wher a code-fetch stalled due to L1 instruction cache miss or iTLB missEMPTYCycles IDQ is emptyMITE_UOPSNumber of uops delivered to IDQ from MITE pathDSB_UOPSNumber of uops delivered to IDQ from DSB pathMS_DSB_UOPSNumber of uops delivered to IDQ when MS busy by DSBMS_MITE_UOPSNumber of uops delivered to IDQ when MS busy by MITEMS_UOPSNumber of uops were delivered to IDQ from MS by either DSB or MITEMITE_UOPS_CYCLESCycles where uops are delivered to IDQ from MITE (MITE active)MITE_UOPS:c=1DSB_UOPS_CYCLESCycles where uops are delivered to IDQ from DSB (DSB active)MS_DSB_UOPS_CYCLESCycles where uops delivered to IDQ when MS busy by DSBMS_DSB_UOPS:c=1MS_MITE_UOPS_CYCLESCycles where uops delivered to IDQ when MS busy by MITEMS_MITE_UOPS:c=1MS_UOPS_CYCLESCycles where uops delivered to IDQ from MS by either BSD or MITEMS_UOPS:c=1ALL_DSB_UOPSNumber of uops delivered from either DSB pathsALL_DSB_CYCLESCycles MITE/MS delivered anythingALL_DSB_CYCLES_4_UOPSCycles MITE/MS delivered 4 uopsALL_MITE_UOPSNumber of uops delivered from either MITE pathsALL_MITE_CYCLESCycles DSB/MS delivered anythingANY_UOPSNumber of uops delivered to IDQ from any pathMS_DSB_UOPS_OCCUROccurences of DSB MS going activeMS_DSB_UOPS:c=1:e=1 0 0$$<CORENumber of non-delivered uops to RAT (use cmask to qualify further) LCPStall caused by changing prefix length of the instructionIQ_FULLStall cycles due to IQ fullANY_PNumber of instructions retiredALLPrecise instruction retired event to reduce effect of PEBS shadow IP distribution (Precise Event)PREC_DIST ITLB_FLUSHNumber of ITLB flushes, includes 4k/2M/4M pagesFLUSH REPLACEMENTNumber of cache lines brought into the L1D cache INT_NOT_ELIMINATEDNumber of integer Move Elimination candidate uops that were not eliminatedSIMD_NOT_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were not eliminatedINT_ELIMINATEDNumber of integer Move Elimination candidate uops that were eliminatedSIMD_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were eliminatedOCCURRENCESOccurrences of L1D_PEND_MISS going activePENDING:e=1:c=1EDGEPENDINGNumber of L1D load misses outstanding every cyclePENDING_CYCLESCycles with L1D load misses outstandingPENDING:c=1HIT_ENon rejected writebacks from L1D to L2 cache lines in E stateHIT_MNon rejected writebacks from L1D to L2 cache lines in M stateMISSNot rejected writebacks that missed LLCNot rejected writebacks from L1D to L2 cache lines in any stateL2 cache lines filling (counting does not cover rejects)EL2 cache lines in E state (counting does not cover rejects)IL2 cache lines in I state (counting does not cover rejects)SL2 cache lines in S state (counting does not cover rejects) DEMAND_CLEANL2 clean line evicted by a demandDEMAND_DIRTYL2 dirty line evicted by a demandPREFETCH_CLEANL2 clean line evicted by a prefetchPF_CLEANPREFETCH_DIRTYL2 dirty line evicted by an MLC PrefetchPF_DIRTYDIRTY_ANYAny L2 dirty line evicted (does not cover rejects)DIRTY_ALL  ALL_CODE_RDAny code request to L2 cacheCODE_RD_HITL2 cache hits when fetching instructionsCODE_RD_MISSL2 cache misses when fetching instructionsALL_DEMAND_DATA_RDDemand data read requests to L2 cacheDEMAND_DATA_RD_HITDemand data read requests that hit L2ALL_PFAny L2 HW prefetch request to L2 cachePF_HITRequests from the L2 hardware prefetchers that hit L2 cachePF_MISSRequests from the L2 hardware prefetchers that miss L2 cacheALL_RFOAny RFO requests to L2 cacheRFO_HITStore RFO requests that hit L2 cacheRFO_MISSRFO requests that miss L2 cache0 @ RFOs that miss cache (I state)RFOs that hit cache lines in M stateRFOs that access cache lines in any state Transactions accessing the L2 pipeCODE_RDL2 cache accesses when fetching instructionsL1D_WBL1D writebacks that access the L2 cacheDMND_DATA_RDDemand Data Read requests that access the L2 cacheL2_FILLL2 fill requests that access the L2 cacheL2_WBL2 writebacks that access the L2 cacheALL_PREFETCHL2 or L3 HW prefetches that access the L2 cache (including rejects)RFORFO requests that access the L2 cache  @STORE_FORWARDLoads blocked by overlapping with store buffer that cannot be forwardedNO_SRNumber of times that split load operations are temporarily blocked because all resources for handlding the split accesses are in useADDRESS_ALIASFalse dependencies in MOB due to partial compare on address HW_PFNon sw-prefetch load dispatches that hit the fill buffer allocated for HW prefetchSW_PFNon sw-prefetch load dispatches that hit the fill buffer allocated for SW prefetchCore-originated cacheable demand requests missed L3REFERENCECore-originated cacheable demand requests that refer to L3AOMASKMOVThe number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0MEMORY_ORDERINGNumber of Memory Ordering Machine Clears detectedSMCSelf-Modifying Code detected XSNP_HITLoad LLC Hit and a cross-core Snoop hits in on-pkg core cache (Precise Event)XSNP_HITMLoad had HitM Response from a core on same socket (shared LLC) (Precise Event)XSNP_MISSLoad LLC Hit and a cross-core Snoop missed in on-pkg core cache (Precise Event)XSNP_NONELoad hit in last-level (L3) cache with no snoop needed (Precise Event)LOCAL_DRAMNumber of retired load uops that missed L3 but were service by local RAM (Precise Event)Number of retired load uops that missed L3 but were service by local RAM, Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded (Precise Event)REMOTE_DRAMNumber of retired load uops that missed L3 but were service by remote RAM, snoop not needed, snoop miss, snoop hit data not forwarded (Precise Event)REMOTE_HITMNumber of retired load uops whose data sources was remote HITM (Precise Event)REMOTE_FWDLoad uops that miss in the L3 whose data source was forwarded from a remote cache (Precise Event) J g gg gHIT_LFBA load missed L1D but hit the Fill Buffer (Precise Event)L1_HITLoad hit in nearest-level (L1D) cache (Precise Event)L2_HITLoad hit in mid-level (L2) cache (Precise Event)L2_MISSLoad misses in mid-level (L2) cache (Precise Event)L3_HITL3_MISSLoad miss in last-level (L3) cache (Precise Event)@ LATENCY_ABOVE_THRESHOLDMemory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)PRECISE_STORECapture where stores occur, must use with PEBS (Precise Event required)ALL_LOADSAny retired loads (Precise Event)ANY_LOADSALL_STORESAny retired stores (Precise Event)LOCK_LOADSLocked retired loads (Precise Event)ANY_STORESSPLIT_LOADSRetired loads causing cacheline splits (Precise Event)SPLIT_STORESRetired stores causing cacheline splits (Precise Event)STLB_MISS_LOADSSTLB misses dues to retired loads (Precise Event)STLB_MISS_STORESSTLB misses dues to retired stores (Precise Event)!ABLOADSSpeculative cache-line split load uops dispatched to the L1DSTORESSpeculative cache-line split Store-address uops dispatched to L1DALL_DATA_RDDemand and prefetch read requests sent to uncoreALL_DATA_READDEMAND_CODE_RDOffcore code read requests, including cacheable and un-cacheablesDEMAND_DATA_RDDemand Data Read requests sent to uncoreDEMAND_RFOOffcore Demand RFOs, includes regular RFO, Locks, ItoMALL_DATA_RD_CYCLESCycles with cacheable data read transactions in the superQALL_DATA_RD:c=1DEMAND_CODE_RD_CYCLESCycles with demand code reads transactions in the superQDEMAND_CODE_RD:c=1DEMAND_DATA_RD_CYCLESCycles with demand data read transactions in the superQDEMAND_DATA_RD:c=1Cacheable data read transactions in the superQ every cycleCode read transactions in the superQ every cycleDemand data read transactions in the superQ every cycleOutstanding RFO (store) transactions in the superQ every cycleDEMAND_RFO_CYCLESCycles with outstanding RFO (store) transactions in the superQDEMAND_RFO:c=1AVX_TO_SSENumber of transitions from AVX-256 to legacy SSE when penalty applicableSSE_TO_AVXNumber of transitions from legacy SSE to AVX-256 when penalty applicableAVX_STORENumber of assists associated with 25-bit AVX storesWBNumber of times the microcode assist is invoked by hardware upon uop writeback Cycles stalled due to Resource Related reasonRSCycles stalled due to no eligible RS entry availableSBCycles stalled due to no store buffers available (not including draining from sync)ROBCycles stalled due to re-order buffer full LBR_INSERTSCount each time an new LBR record is saved by HW EMPTY_CYCLESCycles the RS is empty for this thread LOAD_STLB_HIT DTLB_THREADNumber of DTLB flushes of thread-specific entriesSTLB_ANYNumber of STLB flushes Counts total number of uops executed from any thread per cycleTHREADCounts total number of uops executed per thread each cyclePORT_0Cycles which a Uop is dispatched on port 0PORT_1Cycles which a Uop is dispatched on port 1PORT_2Cycles in which a uop is dispatched on port 2PORT_3Cycles in which a uop is disptached on port 3PORT_4Cycles which a uop is dispatched on port 4PORT_5Cycles which a Uop is dispatched on port 5 0@Number of uops issued by the RAT to the Reservation Station (RS)CORE_STALL_CYCLESCycles no uops issued on this core (by any thread)ANY:c=1:i=1:t=1STALL_CYCLESCycles no uops issued by this threadANY:c=1:i=1FLAGS_MERGENumber of flags-merge uops allocated. Such uops adds delaySLOW_LEANumber of slow LEA or similar uops allocatedSINGLE_MULNumber of multiply packed/scalar single precision uops allocated  @All uops that actually retired (Precise Event)RETIRE_SLOTSNumber of retirement slots used (Precise Event)Cycles no executable uop retired (Precise Event)ALL:c=1:i=1TOTAL_CYCLESTotal cycles using precise uop retired event (Precise Event)ALL:c=16 Request: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesDMND_IFETCHRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesRequest: number of writebacks (modified to exclusive) transactionsPF_DATA_RDRequest: number of data cacheline reads generated by L2 prefetchersPF_RFORequest: number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: number of code reads generated by L2 prefetchersPF_LLC_DATA_RDRequest: number of L3 prefetcher requests to L2 for loadsPF_LLC_RFORequest: number of RFO requests generated by L2 prefetcherPF_LLC_IFETCHRequest: number of L2 prefetcher requests to L3 for instruction fetchesBUS_LOCKSRequest: number bus lock and split lock requestsSTRM_STRequest: number of streaming store requestsOTHERRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCH | PF_LLC_IFETCHPF_IFETCH:DMND_IFETCH:PF_LLC_IFETCHANY_REQUESTRequest: combination of all request umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHERANY_DATARequest: combination of DMND_DATA | PF_DATA_RD | PF_LLC_DATA_RDDMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RDANY_RFORequest: combination of DMND_RFO | PF_RFO | PF_LLC_RFODMND_RFO:PF_RFO:PF_LLC_RFOANY_RESPONSEResponse: count any response typeNO_SUPPSupplier: counts number of times supplier information is not availableLLC_HITMSupplier: counts L3 hits in M-state (initial lookup)LLC_HITESupplier: counts L3 hits in E-stateLLC_HITSSupplier: counts L3 hits in S-stateLLC_HITFSupplier: counts L3 hits in F-stateLLC_MISS_LOCALSupplier: counts L3 misses to local DRAMLLC_MISS_REMOTESupplier: counts L3 misses to remote DRAMLLC_MISS_REMOTE_DRAMLLC_HITMESFSupplier: counts L3 hits in any state (M, E, S, F)LLC_HITM:LLC_HITE:LLC_HITS:LLC_HITFSNP_NONESnoop: counts number of times no snoop-related information is availableSNP_NOT_NEEDEDSnoop: counts the number of times no snoop was needed to satisfy the requestSNP_MISSSnoop: counts number of times a snoop was needed and it missed all snooped cachesSNP_NO_FWDSnoop: counts number of times a snoop was needed and it hit in at leas one snooped cacheSNP_FWDSnoop: counts number of times a snoop was needed and data was forwarded from a remote socketHITMSnoop: counts number of times a snoop was needed and it hitM-ed in local or remote cacheNON_DRAMSnoop: counts number of times target was a non-DRAM system address. This includes MMIO transactionsSNP_ANYSnoop: any snoop reasonSNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAM @D "I @gg< ?Counts the number of times the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end CYCLES_L2_PENDINGCycles with pending L2 miss loadsCYCLES_LDM_PENDINGCycles with pending memory loadsCYCLES_L1D_PENDINGCycles with pending L1D load cache missesCYCLES_NO_EXECUTECycles of dispatch stallsSTALLS_L2_PENDINGExecution stalls due to L2 pending loadsSTALLS_L1D_PENDINGExecution stalls due to L1D pending loadsSTALLS_LDM_PENDINGExecution stalls due to memory loads X87Number of X87 uops executedSSE_FP_PACKED_DOUBLENumber of SSE or AVX-128 double precision FP packed uops executedSSE_FP_SCALAR_SINGLENumber of SSE or AVX-128 single precision FP scalar uops executedSSE_PACKED_SINGLENumber of SSE or AVX-128 single precision FP packed uops executedSSE_SCALAR_DOUBLENumber of SSE or AVX-128 double precision FP scalar uops executed @PACKED_SINGLECounts 256-bit packed single-precisionPACKED_DOUBLECounts 256-bit packed double-precisionUOPSNumber of uops delivered by the Loop Stream Detector (LSD) ARITHCounts arithmetic multiply operationsBACLEARSBranch resteeredBR_INST_EXECBranch instructions executedBR_INST_RETIREDRetired branch instructionsBR_MISP_EXECMispredicted branches executedBR_MISP_RETIREDMispredicted retired branchesBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionBR_INST_RETIRED:ALL_BRANCHESMISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareBR_MISP_RETIRED:ALL_BRANCHESLOCK_CYCLESLocked cycles in L1D and L2CPL_CYCLESUnhalted core cycles at a specific ring levelCPU_CLK_UNHALTEDCycles when processor is not in halted stateDSB2MITE_SWITCHESDSB_FILLDSB fillsDTLB_LOAD_MISSESData TLB load missesDTLB_STORE_MISSESData TLB store missesFP_ASSISTX87 Floating point assistsICACHEInstruction Cache accessesIDQIDQ operationsIDQ_UOPS_NOT_DELIVEREDUops not deliveredILD_STALLInstruction Length Decoder stallsINST_RETIREDInstructions retiredINSTRUCTION_RETIREDNumber of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDITLBInstruction TLBITLB_MISSESInstruction TLB missesL1DL1D cacheMOVE_ELIMINATIONMove EliminationL1D_PEND_MISSL1D pending missesL2_L1D_WB_RQSTSWriteback requests from L1D to L2L2_LINES_INL2 lines alloacatedL2_LINES_OUTL2 lines evictedL2_RQSTSL2 requestsL2_STORE_LOCK_RQSTSL2 store lock requestsL2_TRANSL2 transactionsLAST_LEVEL_CACHE_MISSESThis is an alias for L3_LAT_CACHE:MISSL3_LAT_CACHE:MISSLLC_MISSESAlias for LAST_LEVEL_CACHE_MISSESLAST_LEVEL_CACHE_REFERENCESThis is an alias for L3_LAT_CACHE:REFERENCEL3_LAT_CACHE:REFERENCELLC_REFERENCESAlias for LAST_LEVEL_CACHE_REFERENCESLD_BLOCKSBlocking loadsLD_BLOCKS_PARTIALPartial load blocksLOAD_HIT_PRELoad dispatches that hit fill bufferL3_LAT_CACHECore-originated cacheable demand requests to L3LONGEST_LAT_CACHEMACHINE_CLEARSMachine clear assertedMEM_LOAD_UOPS_LLC_HIT_RETIREDL3 hit loads uops retiredMEM_LOAD_LLC_HIT_RETIREDL3 hit loads uops retired (deprecated use MEM_LOAD_UOPS_LLC_HIT_RETIRED)MEM_LOAD_UOPS_LLC_MISS_RETIREDLoad uops retired that missed the LLCMEM_LOAD_UOPS_RETIREDMemory loads uops retiredMEM_LOAD_RETIREDMemory loads uops retired (deprecated use MEM_LOAD_UOPS_RETIRED)MEM_TRANS_RETIREDMemory transactions retiredMEM_UOPS_RETIREDMemory uops retiredMEM_UOP_RETIREDMemory uops retired (deprecated use MEM_UOPS_RETIRED)MISALIGN_MEM_REFMisaligned memory referencesOFFCORE_REQUESTSOffcore requestsOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsOTHER_ASSISTSCount hardware assistsRESOURCE_STALLSResource related stall cyclesCYCLE_ACTIVITYStalled cyclesROB_MISC_EVENTSReorder buffer eventsRS_EVENTSReservation station eventsDTLB_LOAD_ACCESSTLB accessTLB_ACCESSTLB_FLUSHTLB flushesUNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)UNHALTED_REFERENCE_CYCLESUnhalted reference cyclesUOPS_EXECUTEDUops executedUOPS_DISPATCHED_PORTUops dispatch to specific portsUOPS_ISSUEDUops issuedUOPS_RETIREDUops retiredFP_COMP_OPS_EXECounts number of floating point eventsSIMD_FP_256Counts 256-bit packed floating point instructionsLSDLoop stream detectorOFFCORE_RESPONSE_0Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)OFFCORE_RESPONSE_1?? ?? ????c?\?<????I???y????????Q?X?H?(???$ ?'? ?.A?.A?.O?.O???L?.?.??????? ? ???`???/?^?_?_??<?#???????# ?# ?Intel Ivy BridgeivbIntel Ivy Bridge EPivb_ep;int^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;H Y { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  @ W W W W  #W$X%ret Wl#3W$3X%ret5Wl&HW$Hh Y  {'   Y 1 { ' -F ! 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gZvr$Y2gZvr$Y2Ycntmskpfm_intel_x86_cfgufilterssize_tsizetypepfm_ivb_detectivb_tlb_accessvalidate_pattrsPFM_ATTR_NONEivb_ld_blocks_partialivb_resource_stallsPFM_PMU_NONEpfm_ivbep_detect_IO_save_endPFM_PMU_AMD64ivb_offcore_requestsPFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2ivb_offcore_responseivb_cpl_cyclesPFM_PMU_INTEL_PII_lockivb_l2_rqstsequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtypeintel_ivb_pe_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATivb_move_eliminationPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainpfmlib_intel_ivb.cPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFivb_l1divb_uops_dispatched_portivb_l2_l1d_wb_rqstsPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEivb_lock_cyclesnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countivb_uops_retiredPFM_PMU_MIPS_34Kivb_itlb_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGivb_fp_assistPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXivb_uops_issuedpfm_event_info_tuequivivb_dtlb_store_missesPFM_PMU_PPC970ucntmskivb_rob_misc_eventsPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7intel_ivb_support_IO_FILEivb_tlb_flushivb_cpu_clk_unhaltedos_dataivb_br_inst_execivb_mem_load_uops_llc_miss_retiredpmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlivb_idq_uops_not_deliveredPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000charmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tivb_lsdivb_mem_uops_retiredivb_other_assistsPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posivb_inst_retiredivb_fp_comp_ops_exePFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersivb_rs_eventsPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encoding_flags2pfm_ivb_init_IO_read_baseivb_idqget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endivb_icachePFM_PMU_INTEL_PPROivb_br_inst_retiredumasksivb_l2_transnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3ivb_dsb_fill__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOivb_l2_store_lock_rqstsget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CFivb_dtlb_load_misses_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREivb_ild_stallevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMsteppingcan_auto_encodeivb_simd_fp_256get_event_attr_infoivb_dsb2mite_switchesivb_mem_load_uops_retiredsizeintel_x86_modslong long unsigned intivb_l2_lines_outPFM_DTYPE_CHAR8ivb_misalign_mem_refpattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DPintel_ivb_ep_support__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3ivb_ld_blocks_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descivb_baclearsPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREivb_mem_trans_retired_next__off64_tcodeivb_l2_lines_indtypeivb_arithget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64ivb_br_misp_execshort intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesivb_br_misp_retiredget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_tivb_l3_lat_cachereserved_bitsarch_versionPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endivb_load_hit_prepfm_intel_x86_config_tmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBULivb_offcore_requests_outstanding_filenoivb_l1d_pend_missreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regivb_mem_load_uops_llc_hit_retiredpfm_os_tivb_cycle_activitysupported_plmpfmlib_event_desc_tivb_uops_executedivb_machine_clearsGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx KAC F <KAC F \AC T .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @+ &1; 6@MH?CPa@)T/6ge0b0 {xv 0 >0K-xxx؊HpK   @/ 0CpT@hx PP !$ ', 2P&`344E5N6PV8@k:@}=@@? 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B@(B@pBAxBAB2ABHABlAClACHA`CuAhCApCACACADADADAPDAXDAGDGDPGDXGDGEGEG;EGPE@HwEHHEHEHEHEHE0I,F8I8FIuFI}FIFIF JF(JFK<KpJPKF<XKJK'4KJM'4MKNLN L`NMLhNXLNLNLOLOLPOLXOMO'MO8MOEOEO8M@P|MHPMQPQPQPQPR RR0RSRSRS+SS8ST<T@TUtTUT`V`UhVhUVUVUW*VW.VXPWX`WYWYW`YXhYXYhXYxX\Z\Z\Z\pZ@][H][][][]\] \_0^_8^_r^_^ `^(`^p`^x`_`4_`xXa;_aH_`b`ahbxababbdcdc0e2c8ec@ecexXXx XȮȿ\$8_@>HPPx_`bЯd8d@.H?x`h\m@j~`nư8@r@ݰHxt @)9 vOY8v@tHx wt w@xȱ@'HA[iyw{8 @ȲHղx 0bf8@{Hx D G\ G9 G!) F0 GI7 G> G E GD L G S Ga GTf Gq Gc~ G) G G" G G G Gz G G_ G G+ Gx  G G' G ) G 6 GC GP G] Gj Gw G2 G Gc  G  G] G; G GS G@  G  G  G  G  G - G : G H GRO G[ G]g G s G  G Gq  G  Gd G2 G GA  G GB  G  G  G4 G4 " GA( G. G4 G: G @ GgF G L GuR GnX G^ Gd Gj Gp Gv G | G  G G G  G G G G  GD G  Gm G G; G  G G GQ  G  G  G  G= G  G  Gl  G Gy G  G$ G* G0 G6 G< GB GH GN G T G~[ Gb G i G4p GJw G~ G  G5 G  G G G GZ Gt G G G G G G5 GQ Gm G G G GD  Ga G~ G G& G;- GX4 G ; GB GH I Gg P GWW Gr ^ G e G, l G[s Gz G G G G  G] G G G  G G G G  G` G  Gg G G/ G G G! G' G- GL3 GJ9 G! ? G;E GzL G _ Gde Gik Gq G{x G  G G  G G  G G  G GM G Gf  G Gm1 GK GX Gl G G+ G  G G  G3 G}  G GM G Gf G) Gm6 GP Gj G~ GM G G G  Gi Gl  G% G  G  Go + G7 GC Gw O G[ G`h G u G G G G GM G! Gi GV G G GZ GT G! G8 GD GP G \ G;h Gt G G G G6 G G GL GP Gb G GE GA G G0 G G G G G&  G G=  G1 % G1 G = Gf Z G m GMy G Gf G Gm G8 G G` G Gu G[ G  G G ( G4 GA GIL G2V^Km G  GK G  Gk  G  G2 G>@\ GG h  G G G G2 G9 GF T G a G   G! G-$ G)  '  G ,& G32A G(N`3\ Gi4w G5 G6 G8 G: G= Gr @? G*& B4 GYAGO G4 \Kz Gb M GQ GnR G8S GT G+`V G)X7 GD\b Go_} GG`b Ged GK`h G@j G`n Gz@r G,t: GG vU Gbvp GA} w G@x Gy G{ G  Gs " G/= G J@X Ge@s G  G G] G@ GM GZ G/ G CO @K`/392 1386324440 1009 1009 100664 31552 ` ELF>@@@UHH H}E}tE*t:tijklMISSNumber of snoop missesINVALNumber of snoop invalidates of a non-modified lineHITNumber of snoop hits of a non-modified lineHITMNumber of snoop hits of a modified lineINVAL_MNumber of snoop invalidates of a modified lineANY_SNPNumber of snoopsEXTERNAL_FILTERFilter on cross-core snoops initiated by this Cbox due to external snoop requestXCORE_FILTERFilter on cross-core snoops initiated by this Cbox due to processor core memory requestEVICTION_FILTERFilter on cross-core snoops initiated by this Cbox due to LLC eviction @ STATE_MNumber of LLC lookup requests for a line in modified stateSTATE_ENumber of LLC lookup requests for a line in exclusive stateSTATE_SNumber of LLC lookup requests for a line in shared stateSTATE_INumber of LLC lookup requests for a line in invalid stateSTATE_MESINumber of LLC lookup requests for a lineREAD_FILTERFilter on processor core initiated cacheable read requestsWRITE_FILTERFilter on processor core initiated cacheable write requestsEXTSNP_FILTERFilter on external snoop requestsANY_FILTERFilter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests  @ ALLCounts cycles weighted by the number of requests waiting for data returning from the memory controller, (includes coherent and non-coherent requests initiated by cores, processor graphic units, or LLC) Counts number of coherent and in-coherent requests initiated by cores, processor graphic units, or LLCWRITESCounts the number of allocated write entries, include full, partial, and LLC evictionsEVICTIONSCounts the number of LLC evictions allocated Cycles weighted by number of requests pending in Coherency Tracker Number of requests allocated in Coherency Tracker UNC_CLOCKTICKSuncore clock ticksUNC_CBO_XSNP_RESPONSESnoop responsesUNC_CBO_CACHE_LOOKUPLLC cache lookups" 4 Snoop responses (must provide a snoop type and filter)" 4 UNC_ARB_TRK_OCCUPANCYARB tracker occupancyUNC_ARB_COH_TRK_OCCUPANCYCoherency traffic occupancyUNC_ARB_COH_TRK_REQUESTCoherency traffic requestsIntel Ivy Bridge C-box0 uncoreivb_unc_cbo0uncore_cbox_0Intel Ivy Bridge C-box1 uncoreivb_unc_cbo1uncore_cbox_1Intel Ivy Bridge C-box2 uncoreivb_unc_cbo2uncore_cbox_2Intel Ivy Bridge C-box3 uncoreivb_unc_cbo3uncore_cbox_3:int^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;H Y { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  @ W W W W  #"W$"X%ret$Wl Y  {&  & P  Y  {&   Y  {&  & 6 & P  e {& z U  {& Τ &  U'S 'T 'U 'V ( @ -)( 8"% $ > $ > : ; I  I : ; : ;I8 : ;  : ;  : ; I8 I !I/ &I'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8  : ; !&"'#.: ; 'I@B$: ; I%4: ; I&4: ; I'4: ; I?(4: ; I?<)!,KmJ /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_intel_ivb_unc.ctypes.hstddef.hstdint.hstdio.hlibio.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hintel_snb_unc_events.h "gZvr$Ycntmskpfm_intel_x86_cfgufilterssnb_unc_cbo_xsnp_responsesize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kintel_x86_mods_IO_markerpfmlib_intel_ivb_unc.cPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlPFM_PMU_MIPS_R10000intel_snb_unc_cbo0_pePFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000charmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrintel_ivb_unc_cbo3_supportattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64intel_snb_unc_cbo_pemodhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tpfm_ivb_unc_detectPFM_PMU_AMD64_FAM10H_SHANGHAIsnb_unc_arb_coh_trk_requestuflagslong unsigned intmax_encoding_flags2_IO_read_baseget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endintel_snb_unc_arb_pePFM_PMU_INTEL_PPROintel_ivb_unc_cbo2_supportumasksnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CFsnb_unc_arb_trk_occupancy_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREintel_ivb_unc_cbo0_supportevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEsnb_unc_arb_coh_trk_occupancyPFM_PMU_INTEL_ATOMsteppingcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3snb_unc_cbo_cache_lookup_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsarch_versionintel_ivb_unc_cbo1_supportPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endpfm_intel_x86_config_tmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24Ksnb_unc_arb_trkPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx KAC F .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @KLH+ &M1;: 6TH>C0[T( g%*0bz0 {U*qv{ 0+'0>-? ?8({X?E I@2K` Pe uPP``K   )DSq $Hkpfmlib_intel_ivb_unc.csnb_unc_cbo_xsnp_responsesnb_unc_cbo_cache_lookupsnb_unc_arb_trk_occupancysnb_unc_arb_trksnb_unc_arb_coh_trk_occupancysnb_unc_arb_coh_trk_requestintel_snb_unc_cbo0_peintel_snb_unc_cbo_peintel_snb_unc_arb_pepfm_ivb_unc_detectpfm_intel_x86_detectpfm_intel_x86_cfgintel_ivb_unc_cbo0_supportintel_x86_modspfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_get_event_attr_infopfm_intel_x86_get_encodingpfm_intel_nhm_unc_get_perf_encodingpfm_intel_x86_perf_validate_pattrspfm_intel_x86_perf_detectpfm_intel_x86_validate_tableintel_ivb_unc_cbo1_supportintel_ivb_unc_cbo2_supportintel_ivb_unc_cbo3_support !3@_l@`HPhpx !"##$$%%&@`HPhpx !"##$$%%&@`HPhpx !"##$$%%&,@`HPhpx !"##$$%%&@H([`08 ( pqxS`@H*80 a8 p     *( 8` p h x p      ` w h  p  p P`h(@8M`h @8M`  &BZ8    ~!K) 0 7 (>  E L S +a Uf g q ~ C U <   Y   }     Z Z )  6 C P ] wj w    Y      e          -  : H O [  g ! s M j  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'  - 3 }9 F? ) E yL > _  e k q x        '  E       1 K X  l    '  E ! 4   ;     ) 6  P j ~          & `    + 7 C  O 6[ 9 h  u h      j   R    !  8 5D NP  \ h nt   $ f   j L  C u A       e    V% b1 @=  Z H m y     ]    t   Z  ( S4  A L DV^Km  "@   `   "  .< uHf r` +` h  K  `'  ( ) .  W /416 1386324440 1009 1009 100664 102352 ` ELF>h@@UHH H}E}tE*t?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;H Y { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  @ W W W W  #W$X%ret Wl&3W$3h Y  {'   Y  { ' #  Y  {' g2   Y G {' \ 7 Y q {'  a' ʠ a Y  {'   Y  {'   Y  {(  ( 4: 7 Y O {( _e ?(   Y  {(  (  (  (  (  ( &2 ( .M a( Gh  Y } {( O m( l ( y (  7(  (  ( 5 ( P ( &k ( 3 a( E ( \ ( d  (  (   7( ( ( C ( ^ ( y a(  m( - ( 5 ( = ( J ( Y ( 6  ( Q   Y f { ( | V(  7(  7(   ( F ( ] 7(  ( 9 7( T  i {@(  Y)9 * @ +* % $ > $ > : ; I  I : ; : ;I8 : ;  : ;  : ; I8 I !I/ &I'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8  : ; !&"'#.: ; 'I@B$: ; I%4: ; I&.: ; 'I@B'4: ; I(4: ;I)4: ; I?*4: ; I?<+!,diB /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_intel_hsw.ctypes.hstddef.hstdint.hstdio.hlibio.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hintel_hsw_events.h gZvr$Y2Ycntmskpfm_intel_x86_cfgufilterssize_thsw_rtm_retiredsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEhsw_l2_rqsts_IO_save_endPFM_PMU_AMD64hsw_offcore_requestshsw_icachePFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2hsw_page_walker_loadsintel_hsw_supportPFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtypehsw_move_elimination_IO_save_basehsw_br_misp_execPFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kintel_x86_mods_IO_markerhsw_load_hit_prePFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateintel_hsw_peunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXhsw_mem_load_uops_retiredhsw_hle_retiredctrlhsw_rob_misc_eventshsw_itlbPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000hsw_offcore_requests_outstandingcharmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERhsw_fp_assisthsw_resource_stallsPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KChsw_idq_uops_not_delivered_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3hsw_tlb_flush_markersPFM_ATTR_MAXhsw_mem_load_uops_l3_hit_retiredPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIhsw_l2_transuflagslong unsigned intmax_encoding_flags2_IO_read_basehsw_offcore_responseget_event_nexthsw_uops_retiredthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodehsw_rs_eventsPFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64hsw_mem_uops_retiredPFM_PMU_I386_PMlong long intpfmlib_attr_desc_thsw_br_inst_exechsw_itlb_missesunamehsw_cpl_cyclesPFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1hsw_mem_load_uops_l3_miss_retiredintel_x86_umask_t_IO_write_endhsw_cpu_clk_thread_unhaltedPFM_PMU_INTEL_PPROumaskshsw_longest_lat_cachepfm_hsw_detectnpattrscountdfl_boolevent_IO_buf_baseunsigned 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intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_namehsw_l1d_pend_missis_dflhsw_idqPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_thsw_ild_stallcodehsw_tx_memhsw_br_misp_retireddtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKhsw_l2_demand_rqstsPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Iosidhsw_br_inst_retiredhsw_lsdPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_firstpfm_hsw_init/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsarch_versionhsw_uops_issuedhsw_ld_blocksPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endpfm_intel_x86_config_tmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedhsw_tx_execPFM_PMU_INTEL_NHM_EXshort unsigned inthsw_cycle_activitydfl_intvalidate_tablepmu_revhsw_ld_blocks_partial_IO_write_ptrPFM_PMU_INTEL_SNB_EPhsw_lock_cyclesPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_reghsw_l2_lines_outpfm_os_tsupported_plmpfmlib_event_desc_tpfmlib_intel_hsw.chsw_other_assistshsw_inst_retiredGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx KAC F <AC T .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @d0`+ &1; 6XLHCf(TR6g0bX0 {mv 0%0!-NPX0( @I h@P!2 0FWkz@" %P,2P 3@5(6P1@7P9 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-mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsfilterarch_versionis_occ_eventPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endpfm_intel_x86_config_tmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBULpfm_intel_snbep_unc_detect_filenoreservedPFM_PMU_INTEL_NHM_EXintel_x86_attr2umaskshort unsigned intunc_edgedfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPintel_x86_uflagPFM_DTYPE_FIXEDpcu_filt_bandnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KgrpcountsPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regcbo_filtpfm_os_tsupported_plmpfmlib_event_desc_tuidxpfmlib_intel_snbep_unc.chi_addrGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx ?AC z <~AC y \]AC X |AC  sAC n FAC A AC  hAC c \AC W < AC [ \AC   |AC H TAC O  #AC  .symtab.strtab.shstrtab.rela.text.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @*i &l,l6 1 s`Cg#>v-O><b1B0]@0 vaBfqp 0F0[-[[P]c g?*?~9]I^ssp.h\ !   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Includes all write transactions (cached, uncached)REMOTE_SNOOPExternal snoop requestNIDMatch a given RTID destination NIDSTATE_IInvalid cacheline stateSTATE_SShared cacheline stateSTATE_EExclusive cacheline stateSTATE_MModified cacheline stateSTATE_FForward cacheline stateSTATE_MESIFAny cache line state A@ @| M_STATELines in M stateE_STATELines in E stateS_STATELines in S stateMISSTBDVictimized Lines matching the NID filter@RSPI_WAS_FSESilent snoop evictionWC_ALIASINGWrite combining aliasingSTARTEDRFO_HIT_SRFO hits in S stateUP_EVENUp and Even ring polarity filterUP_ODDUp and odd ring polarity filterDOWN_EVENDown and even ring polarity filterDOWN_ODDDown and odd ring polarity filterAK_COREAcknowledgment to coreBL_COREData response to coreIV_CORESnoops of processor cacheANYAny filterIRQIrq externally starved, therefore blocking the IPQIPQIPQ externally starved, therefore blocking the IRQISMQISMQ externally starved, therefore blocking both IRQ and IPQISMQ_BIDSNumber of time the ISMQ bidsIRQ_REJECTEDIRQ rejectedVFIFOCounts the number of allocated into the IRQ ordering FIFOADDR_CONFLICTAddress conflictAny RejectFULLNo Egress creditsQPI_CREDITSNo QPI credits Any rejectRTIDNo RTIDs IIO_CREDITSNo IIO creditsNO QPI credits  Number of used entries in the IRQ ordering FIFO in each cycleEVICTIONNumber of Evictions transactions inserted into TORMISS_ALLNumber of miss requests inserted into the TORMISS_OPCODENumber of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)NID_ALLNumber of NID-matched transactions inserted into the TORNID_EVICTIONNumber of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)NID_MISS_ALLNumber of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)NID_MISS_OPCODENumber of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)NID_OPCODENumber of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)NID_WBNumber of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)OPCODENumber of transactions inserted into the TOR that match an opcode (must provide opc_* umask)WBNumber of write transactions inserted into the TOROPC_RFODemand data RFO (combine with any OPCODE umask)OPC_CRDDemand code read (combine with any OPCODE umask)OPC_DRDDemand data read (combine with any OPCODE umask)OPC_PRDPartial reads (UC) (combine with any OPCODE umask)OPC_WCILFFull Stream store (combine with any OPCODE umask)OPC_WCILPartial Stream store (combine with any OPCODE umask)OPC_PF_RFOPrefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_CODEPrefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_DATAPrefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PCIWILFPCIe write (non-allocating) (combine with any OPCODE umask)OPC_PCIPRDPCIe UC read (combine with any OPCODE umask)OPC_PCIITOMPCIe write (allocating) (combine with any OPCODE umask)OPC_PCIRDCURPCIe read current (combine with any OPCODE umask)OPC_WBMTOIRequest writeback modified invalidate line (combine with any OPCODE umask)OPC_WBMTOERequest writeback modified set to exclusive (combine with any OPCODE umask)OPC_ITOMRequest invalidate line (combine with any OPCODE umask)OPC_PCINSRDPCIe non-snoop read (combine with any OPCODE umask)OPC_PCINSWRPCIe non-snoop write (partial) (combine with any OPCODE umask)OPC_PCINSWRFPCIe non-snoop write (full) (combine with any OPCODE umask)A AHA@DA@JA@C@A@PA@AALLAll valid TOR entriesNumber of outstanding eviction transactions in the TORNumber of outstanding miss requests in the TORNumber of TOR entries that match a NID and an opcode (must provide opc_* umask)Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)Number of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)Number of TOR entries that match an opcode (must provide opc_* umask)IA AHA@DA@JA@C@A@AD_CACHECounts the number of ring transactions from Cachebo to AD ringAK_CACHECounts the number of ring transactions from Cachebo to AK ringBL_CACHECounts the number of ring transactions from Cachebo to BL ringIV_CACHECounts the number of ring transactions from Cachebo ton IV ringAD_CORECounts the number of ring transactions from Corebo to AD ringCounts the number of ring transactions from Corebo to AK ringCounts the number of ring transactions from Corebo to BL ring @UNC_C_CLOCKTICKSC-box Uncore clockticksUNC_C_COUNTER0_OCCUPANCYCounter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.UNC_C_ISMQ_DRD_MISS_OCCUNC_C_LLC_LOOKUPCache lookups. Counts number of times the LLC is accessed from L2 for code, data, prefetches (Must set filter mask bit 0 and select )UNC_C_LLC_VICTIMSLines victimizedUNC_C_MISCMiscelleanous C-Box eventsUNC_C_RING_AD_USEDAddress ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_AK_USEDAcknowledgement ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_BL_USEDBus or Data ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_BOUNCESNumber of LLC responses that bounced in the ringUNC_C_RING_IV_USEDInvalidate ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_SRC_THRTLTDBUNC_C_RXR_EXT_STARVEDIngress arbiter blockig cyclesUNC_C_RXR_INSERTSIngress AllocationsUNC_C_RXR_IPQ_RETRYProbe Queue RetriesUNC_C_RXR_IRQ_RETRYIngress Request Queue RejectsUNC_C_RXR_ISMQ_RETRYISMQ RetriesUNC_C_RXR_OCCUPANCYIngress OccupancyUNC_C_TOR_INSERTSTOR InsertsUNC_C_TOR_OCCUPANCYTOR OccupancyUNC_C_TXR_ADS_USEDEgress eventsUNC_C_TXR_INSERTSEgress allocations7!74 w7797 7 7 77 777717273775w6w77[UNC_CBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d] %s [UNC_CBOX_FILTER=0x%lx tid=%d core=0x%x nid=0x%x state=0x%x opc=0x%x] Intel Sandy Bridge-EP C-Box 0 uncoresnbep_unc_cbo0uncore_cbox_0Intel Sandy Bridge-EP C-Box 1 uncoresnbep_unc_cbo1uncore_cbox_1Intel Sandy Bridge-EP C-Box 2 uncoresnbep_unc_cbo2uncore_cbox_2Intel Sandy Bridge-EP C-Box 3 uncoresnbep_unc_cbo3uncore_cbox_3Intel Sandy Bridge-EP C-Box 4 uncoresnbep_unc_cbo4uncore_cbox_4Intel Sandy Bridge-EP C-Box 5 uncoresnbep_unc_cbo5uncore_cbox_5Intel Sandy Bridge-EP C-Box 6 uncoresnbep_unc_cbo6uncore_cbox_6Intel Sandy Bridge-EP C-Box 7 uncoresnbep_unc_cbo7uncore_cbox_7Zint^^B1 N W     ( 0 8 @  H !P "X $` &h (Wp ,Wt .ex 24 3I 4 8 Ap J K L M N PW R     WU{N{W8BC      !"#$%&'()*+,-./0123456789:;<=>?ίR~]12;3;@&r ' ( ) * + pmu,( -R,idx.W0 /W4 0W8<5@A;B;C;EFGHWIW@7p 8 9 : ; < =(idx>W, ?~0~48K5 6 7 89|@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ]!  ^' ( _7 ( `H!e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pes@ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]   ! {?p7 {G {aX "n c W Wt W W r ; W W WW W WW!  : {W4 4 G  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;HY { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  \# ]B8# ^B0# _B/# `B.# aB-# bB*# cB)# dB(# eB # fB  hT# iB8# jB0# kB/# lB.# mB-# nB,# oB*# pB)# qB(# rB # sB  u># vB8# wB2# xB0# yB/# zB.# {B-# |B,# }B*# ~B)# B(# B## B"# B!# B # B  # B8# B0# B/# B.# B-# B,# B+# B*# B)# B(# B # B  $tid B?$cid B<# B;# B8# B6$nid B.# B)$opc B # B# B  # B8# B0# B(# B # B  3# B:# B # B# B i$opc B:# B # B  Z%val [%com g%cbo t%pcu T%qpi >    3 i&%N'%H(e%4 @(val%)pe'Nh)reg(Y`)f)PT Y o{ *  _Y {*  Y {*  *  Y {*  Y 1{+ G !+ b + (} + ? + V + r +  Y {+  Y ){+ ? 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intPFM_PMU_SPARC_ULTRA3intel_snbep_unc_cb7_support__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOunc_event_extget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOunc_occ_invPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREpfmlib_intel_snbep_unc_cbo.cPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMsnbep_unc_c_rxr_ext_starvedcan_auto_encodeget_event_attr_infosizelong long unsigned intintel_snbep_unc_cb3_supportPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64unc_rstPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12unc_thresPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descsnbep_unc_c_tor_occupancyPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Isnbep_unc_modsosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_firstsnbep_unc_c_ring_bounces/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetunc_tidPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_tdisplay_cboreserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAXsnbep_unc_c_ring_ad_used_IO_read_endmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenointel_snbep_unc_cb4_supportreservedPFM_PMU_INTEL_NHM_EXshort unsigned intunc_edgedfl_intvalidate_tablepmu_revintel_snbep_unc_c_pe_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regcbo_filtpfm_os_tsupported_plmsnbep_unc_c_llc_victimspfmlib_event_desc_thi_addrGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx MAC H .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @M`+ &1 ; G 6HQ^C'Tg`gXj0b0 {jv 0Yl%0~-8h `1 5@M@@^@ @w  P @@`@,`@F ` ^- x80?M   $A^}'Pmpfmlib_intel_snbep_unc_cbo.csnbep_unc_c_llc_lookupsnbep_unc_c_llc_victimssnbep_unc_c_miscsnbep_unc_c_ring_ad_usedsnbep_unc_c_ring_bouncessnbep_unc_c_ring_iv_usedsnbep_unc_c_rxr_ext_starvedsnbep_unc_c_rxr_insertssnbep_unc_c_rxr_ipq_retrysnbep_unc_c_rxr_irq_retrysnbep_unc_c_rxr_ismq_retrysnbep_unc_c_rxr_occupancysnbep_unc_c_tor_insertssnbep_unc_c_tor_occupancysnbep_unc_c_txr_insertsintel_snbep_unc_c_pedisplay_cbo__pfm_vbprintfintel_snbep_unc_cb0_supportsnbep_unc_modspfm_intel_snbep_unc_detectpfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_can_auto_encodepfm_intel_snbep_unc_get_event_attr_infopfm_intel_snbep_unc_get_encodingpfm_intel_snbep_unc_get_perf_encodingpfm_intel_snbep_unc_perf_validate_pattrspfm_intel_x86_validate_tableintel_snbep_unc_cb1_supportintel_snbep_unc_cb2_supportintel_snbep_unc_cb3_supportintel_snbep_unc_cb4_supportintel_snbep_unc_cb5_supportintel_snbep_unc_cb6_supportintel_snbep_unc_cb7_support  E= xEGEEE@?H!P"h#p$x%&'()*++,,-F-FB B7>BI>C C]>(Cq>XC``C>hC>CC>C>CC>C>D D>(D?XD `D?hD1?D-D??DR?D`?Dr?E8     ;!M) 0 e7 > 6 E  L S a f q ~  0  x S  F   d    ?#  0 ) = J W d gq ~        e * 8  t  {     '  4 * A , O V kb n  z 3  Z 2  z  |  t     i @  C  #  ) &/  5  ; A G xM S Y )_ Ze "k q w } P      |     G   C        _      i     \   \ % + v1 7 = C I O =U k [ b Ci Yp Rw |~    M   o o      v 4      *   b   & $- 4 ;  B I P W s^  e 6 l  s z   " < '  #        2 T  0     V  "  ( . 4 : b@ eF L 9S  f l r Tx  0   d   @     y P V s 8 R _ s G y    U      y  P V# s0 = W q  y P  a  $ -   5 # &  2 > J  V b o r |   O w P y o /   " r   ( ? K W  c Wo {  w   O _   #   H   \ t v X n      u% 1 _=  Z  m yy P V   |  q J 4   ~ m. = L [ j 9y c    ~ m    t   9' c 6 E ] ~l {       9 c    P  / G ~V me t       9 c   " ;1 @@ E^  | J O         @ @   $ EK @Z E          M ' p | @ @ K@  " 2 ? M 3Z h >u ` 8 5  @`   * U7-U 2b8 *? >  .  / 0 1 2 %3. X :4N   /492 1386324440 1009 1009 100664 39792 ` ELF>T@@UHH`H}HuHUHEH@@HEHEHEHEЋ@ HHHHEHLHE@HE@HE@DHE@DHE@HEHEHLD$|$4$EHƿHEЋ@tgHEH0HEEf%?ȋEHEHƿHEH8HEE?HEHƿXCONFLICTNumber of cycles that we are handling conflictsNO_CONFLICTNumber of cycles that we are not handling conflictsNO_SNPSnoop not neededSNPSnoop neededANYCounts any directory updateCLEARDirectory clearsSETDirectory set AD_QPI0AD to QPI link 0AD_QPI1AD to QPI link 1BL_QPI0BL to QPI link 0BL_QPI1BL to QPI link 1ALLCounts all writesFULLCounts full line non ISOCHFULL_ISOCHCounts ISOCH full linePARTIALCounts partial non-ISOCHPARTIAL_ISOCHCounts ISOCH partial READSCounts incoming read requests. Good proxy for LLC read misses, incl. RFOsWRITESCounts incoming writes CHN0Channel 0CHN1Channel 1CHN2channel 2CHN3Chanell 3REGION0Counts for TAD Region 0REGION1Counts for TAD Region 1REGION2Counts for TAD Region 2REGION3Counts for TAD Region 3REGION4Counts for TAD Region 4REGION5Counts for TAD Region 5REGION6Counts for TAD Region 6REGION7Counts for TAD Region 7 @REGION8Counts for TAD Region 8REGION9Counts for TAD Region 9REGION10Counts for TAD Region 10REGION11Counts for TAD Region 11Counts all requests NDRCounts non-data responsesCounts outbound snoops send on the ringCounts cycles full from both schedulersSCHED0Counts cycles full from scheduler bank 0SCHED1Counts cycles full from scheduler bank 1 Counts cycles from both schedulersCounts cycles from scheduler bank 0Counts cycles from scheduler bank 1 DRS_CACHECounts data being sent to the cacheDRS_CORECounts data being sent directly to the requesting coreDRS_QPICounts data being sent to a remote socket over QPIHA iMC CHN0 WPQ Credits Empty - RegularBL Egress FullUNC_H_CLOCKTICKSHA Uncore clockticksUNC_H_CONFLICT_CYCLESConflict ChecksUNC_H_DIRECT2CORE_COUNTDirect2Core Messages SentUNC_H_DIRECT2CORE_CYCLES_DISABLEDCycles when Direct2Core was DisabledUNC_H_DIRECT2CORE_TXN_OVERRIDENumber of Reads that had Direct2Core OverriddenUNC_H_DIRECTORY_LOOKUPDirectory LookupsUNC_H_DIRECTORY_UPDATEDirectory UpdatesUNC_H_IGR_NO_CREDIT_CYCLESCycles without QPI Ingress CreditsUNC_H_IMC_RETRYRetry EventsUNC_H_IMC_WRITESHA to iMC Full Line Writes IssuedUNC_H_REQUESTSRead and Write RequestsUNC_H_RPQ_CYCLES_NO_REG_CREDITSiMC RPQ Credits Empty - RegularUNC_H_TAD_REQUESTS_G0HA Requests to a TAD Region - Group 0UNC_H_TAD_REQUESTS_G1HA Requests to a TAD Region - Group 1UNC_H_TRACKER_INSERTSTracker AllocationsUNC_H_TXR_ADOutbound NDR Ring TransactionsUNC_H_TXR_AD_CYCLES_FULLAD Egress FullUNC_H_TXR_AK_CYCLES_FULLAK Egress FullUNC_H_TXR_AK_NDRUNC_H_TXR_BLOutbound DRS Ring Transactions to CacheUNC_H_TXR_BL_CYCLES_FULLUNC_H_WPQ_CYCLES_NO_REG_CREDITS   "*26[UNC_HA=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s [UNC_HA_ADDR=0x%lx lo_addr=0x%x hi_addr=0x%x] [UNC_HA_OPC=0x%lx opc=0x%x] Intel Sandy Bridge-EP HA uncoresnbep_unc_hauncore_haint^^B1 N W     ( 0 8 @  H !P "X $` &h (Wp ,Wt .ex 24 3I 4 8 Ap J K L M N PW R     WU{N{W8BC      !"#$%&'()*+,-./0123456789:;<=>?ίR~]12;3;@&r ' ( ) * + pmu,( -R,idx.W0 /W4 0W8<5@A;B;C;EFGHWIW@7p 8 9 : ; < =(idx>W, ?~0~48K5 6 7 89|@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ]!  ^' ( _7 ( `H!e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pes@ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]   ! {?p7 {G {aX "n c W Wt W W r ; W W WW W WW!  : {W4 4 G  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;HY { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  \# ]B8# ^B0# _B/# `B.# aB-# bB*# cB)# dB(# eB # fB  hT# iB8# jB0# kB/# lB.# mB-# nB,# oB*# pB)# qB(# rB # sB  u># vB8# wB2# xB0# yB/# zB.# {B-# |B,# }B*# ~B)# B(# B## B"# B!# B # B  # B8# B0# B/# B.# B-# B,# B+# B*# B)# B(# B # B  $tid B?$cid B<# B;# B8# B6$nid B.# B)$opc B # B# B  # B8# B0# B(# B # B  3# B:# B # B# B i$opc B:# B # B  Z%val [%com g%cbo t%pcu T%qpi >    3 i&%N'%H(e%4 @(val%)pe'Nh)reg(Y`)f)PT Y o{*  _* + _Y {* 8 Y {* J Y {* a * }6 _* P Y e{* z U* ̔ Y {*  *  _*  +   + ( + .C + E^  s{+ a c,C -. % $ > $ > : ; I  I&I&  : ; : ;I8 : ;  : ;  : ; I8 I!I/ 'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8! : ; "'# : ; I 8 $ : ; I 8 % : ; I&.: ; '@B': ; I(: ; I)4: ; I*4: ; I+4: ;I,4: ; I?-!.4: ; I?<,1u /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_intel_snbep_unc_ha.ctypes.hstddef.hstdio.hlibio.hstdint.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hpfmlib_intel_snbep_unc_priv.hintel_snbep_unc_ha_events.h %= wfDxCyBzON~?q>H $>dycntmskufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2unc_res1unc_res2unc_res3unc_res4unc_res5unc_res6statePFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtypesnbep_unc_h_igr_no_credit_cycles_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFres0res1res2res3res4PFM_ATTR_CTRL_PERF_EVENTunc_umaskget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countunc_enPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmsksnbep_unc_h_conflict_cyclesPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEsnbep_unc_h_txr_blos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXunc_occctrlunc_occ_edgePFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000chardfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pnameunc_event_IO_lock_tsnbep_unc_h_wpq_cycles_no_reg_creditsPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERpcu_filtPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_possnbep_unc_h_txr_adPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tunc_invPFM_PMU_AMD64_FAM10H_SHANGHAIfilt0filt1filt2filt3uflagslong unsigned intmax_encodingha_addrpfm_snbep_unc_reg_t_flags2_IO_read_baseha_opcget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endPFM_PMU_INTEL_PPROsnbep_unc_h_imc_writesumaskslo_addrnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOunc_event_extget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOunc_occ_invPFM_PMU_INTEL_WSM_UNCfstrsnbep_unc_h_txr_ak_cycles_fullpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64unc_rstPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12unc_thressnbep_unc_h_directory_updatePFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrssnbep_unc_h_rpq_cycles_no_reg_creditsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Isnbep_unc_modsosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMsnbep_unc_h_txr_bl_cycles_fullpmu_detectuint64_tgrpidcodesget_event_firstsnbep_unc_h_tracker_inserts/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetunc_tidPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_tsnbep_unc_h_requestsintel_snbep_unc_ha_supportreserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUsnbep_unc_h_txr_ad_cycles_fullPFM_OS_MAX_IO_read_endmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBULintel_snbep_unc_h_pe_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intunc_edgedfl_intvalidate_tablepmu_revsnbep_unc_h_tad_requests_g0snbep_unc_h_tad_requests_g1_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regcbo_filtpfm_os_tsupported_plmpfmlib_event_desc_tdisplay_hapfmlib_intel_snbep_unc_ha.csnbep_unc_h_directory_lookuphi_addrGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx 1AC , .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @1b+ &c1;o" 6dH$Cpt&T:`g=0b0 {>=v@ 0>0S-SS8XTZP  ^9Vs@@ @`P:M@l@ 1   -<Wu .T}pfmlib_intel_snbep_unc_ha.csnbep_unc_h_conflict_cyclessnbep_unc_h_directory_lookupsnbep_unc_h_directory_updatesnbep_unc_h_igr_no_credit_cyclessnbep_unc_h_imc_writessnbep_unc_h_requestssnbep_unc_h_rpq_cycles_no_reg_creditssnbep_unc_h_tad_requests_g0snbep_unc_h_tad_requests_g1snbep_unc_h_tracker_insertssnbep_unc_h_txr_adsnbep_unc_h_txr_ad_cycles_fullsnbep_unc_h_txr_ak_cycles_fullsnbep_unc_h_txr_blsnbep_unc_h_wpq_cycles_no_reg_creditssnbep_unc_h_txr_bl_cycles_fullintel_snbep_unc_h_pedisplay_ha__pfm_vbprintfintel_snbep_unc_ha_supportsnbep_unc_modspfm_intel_snbep_unc_detectpfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_get_event_attr_infopfm_intel_snbep_unc_get_encodingpfm_intel_snbep_unc_get_perf_encodingpfm_intel_snbep_unc_perf_validate_pattrspfm_intel_x86_validate_table ! ! ! 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" %.< Hf hr   :`  @ }   . ;I Vt   :!   /521 1386324440 1009 1009 100664 32232 ` ELF>D@@YZ[\ALLCounts total number of DRAM CAS commands issued on this channelRDCounts all DRAM reads on this channel, incl. underfillsRD_REGCounts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit prechargeRD_UNDERFILLCounts number of underfill reads issued by the memory controllerWRCounts number of DRAM write CAS commands on this channelWR_RMMCounts Number of opportunistic DRAM write CAS commands issued on this channelWR_WMMCounts number of DRAM write CAS commands issued on this channel while in Write-Major mode  HIGHTBDPANICISOCHCounts cycles in ISOCH Major maodePARTIALCounts cycles in Partial Major modeREADCounts cycles in Read Major modeWRITECounts cycles in Write Major modeRANK0Count cycles for rank 0RANK1Count cycles for rank 1RANK2Count cycles for rank 2RANK3Count cycles for rank 3RANK4Count cycles for rank 4RANK5Count cycles for rank 5RANK6Count cycles for rank 6RANK7Count cycles for rank 7 @RD_PREEMPT_RDCounts read over read preemptionsRD_PREEMPT_WRCounts read over write preemptionsPAGE_CLOSECounts number of DRAM precharge commands sent on this channel as a result of the page close counter expiringPAGE_MISSCounts number of DRAM precharge commands sent on this channel as a result of page missesUNC_M_CLOCKTICKSIMC Uncore clockticksUNC_M_ACT_COUNTDRAM Activate CountUNC_M_CAS_COUNTDRAM RD_CAS and WR_CAS Commands.UNC_M_DRAM_PRE_ALLDRAM Precharge All CommandsUNC_M_DRAM_REFRESHNumber of DRAM Refreshes IssuedUNC_M_ECC_CORRECTABLE_ERRORSECC Correctable ErrorsUNC_M_MAJOR_MODESCycles in a Major ModeUNC_M_POWER_CHANNEL_DLLOFFChannel DLLOFF CyclesUNC_M_POWER_CHANNEL_PPDChannel PPD CyclesUNC_M_POWER_CKE_CYCLESCKE_ON_CYCLES by RankUNC_M_POWER_CRITICAL_THROTTLE_CYCLESCritical Throttle CyclesUNC_M_POWER_SELF_REFRESHClock-Enabled Self-RefreshUNC_M_POWER_THROTTLE_CYCLESThrottle Cycles for Rank 0UNC_M_PREEMPTIONRead Preemption CountUNC_M_PRE_COUNTDRAM Precharge commands.UNC_M_RPQ_CYCLES_FULLRead Pending Queue Full CyclesUNC_M_RPQ_CYCLES_NERead Pending Queue Not EmptyUNC_M_RPQ_INSERTSRead Pending Queue AllocationsUNC_M_RPQ_OCCUPANCYRead Pending Queue OccupancyUNC_M_WPQ_CYCLES_FULLWrite Pending Queue Full CyclesUNC_M_WPQ_CYCLES_NEWrite Pending Queue Not EmptyUNC_M_WPQ_INSERTSWrite Pending Queue AllocationsUNC_M_WPQ_OCCUPANCYWrite Pending Queue OccupancyUNC_M_WPQ_READ_HITWrite Pending Queue CAM MatchUNC_M_WPQ_WRITE_HIT CA"! #$Intel Sandy Bridge-EP IMC0 uncoresnbep_unc_imc0uncore_imc_0Intel Sandy Bridge-EP IMC1 uncoresnbep_unc_imc1uncore_imc_1Intel Sandy Bridge-EP IMC2 uncoresnbep_unc_imc2uncore_imc_2Intel Sandy Bridge-EP IMC3 uncoresnbep_unc_imc3uncore_imc_3iintNNz2z1 > G t t t t t( t0 t8 t@  tH !tP "tX $v` &|h (Gp ,Gt .Ux 2$ 39 4 8 A` Jr Kr Lr Mr N PG R  v v | GEzk>zkGr82C      !"#$%&'()*+,-./0123456789:;<=>?ΟB nMy12+3+@&b ' ( ) * + pmu,( -B,idx.G0 /G4 0G8<5@A+B+C+EFGHGIG@7` 8 9 : ; < =(idx>G, ?n0n48K5 6 7 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/usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventstypes.hstddef.hstdio.hlibio.hstdint.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hintel_snbep_unc_imc_events.hpfmlib_intel_snbep_unc_imc.cpfmlib_intel_snbep_unc_priv.hcntmskufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTintel_snbep_unc_imc0_supportPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATsnbep_unc_m_power_cke_cyclesPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEsnbep_unc_m_pre_countos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000chardfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tsnbep_unc_m_preemptionPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflagsintel_snbep_unc_imc1_support_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encoding_flags2_IO_read_baseintel_snbep_unc_m_peget_event_next_unused2snbep_unc_m_major_modesPFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescintel_snbep_unc_imc3_supportPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endPFM_PMU_INTEL_PPROumasksnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREintel_snbep_unc_imc2_supportPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64snbep_unc_modsPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3snbep_unc_m_dram_refresh_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfmlib_intel_snbep_unc_imc.cpfm_attr_treserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endmodmsksnbep_unc_m_cas_countPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2).symtab.strtab.shstrtab.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.debug_line.debug_str.comment.note.GNU-stack@&@ !N,@6@~ 1U Cm>_0O+-b. ]} q/}000=C-jCjCH` 0L`04M@e@@  @@     )Fc1Nkpfmlib_intel_snbep_unc_imc.csnbep_unc_m_cas_countsnbep_unc_m_dram_refreshsnbep_unc_m_major_modessnbep_unc_m_power_cke_cyclessnbep_unc_m_preemptionsnbep_unc_m_pre_countintel_snbep_unc_m_peintel_snbep_unc_imc0_supportsnbep_unc_modspfm_intel_snbep_unc_detectpfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_get_event_attr_infopfm_intel_snbep_unc_get_encodingpfm_intel_snbep_unc_get_perf_encodingpfm_intel_snbep_unc_perf_validate_pattrspfm_intel_x86_validate_tableintel_snbep_unc_imc1_supportintel_snbep_unc_imc2_supportintel_snbep_unc_imc3_support@@HPhpx @@HPhpx "1@@HPhpx @bq@@HPhpx `hHPP XY`@H@HPkXx@@HF^d|0 8      ( p x @  H      0 ] 8 h @ H     `@0HHxh@H!8@Pu@Hx@ @  0 I`@H0@PHd@H  ^    ' .  5 O< C Q cV  a n } =    W n I $ , v w  V   - : G 4T Ka n {  n U   = D  K          $ r 1 ? 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JE *K mR N Y d ` Mg Ln u  |    o  I         N     6 R  ] z    "$ ?+  2 9 S@ rG N \ U \ g c j q x " <  l        =   0 F     V   +    $ * 0 ,6  < aC : V A \ b h o x    B ! u     j    ( B O c ox       B     j    - G a u  j       4 B   ~ " . :  F 1R  _  l y   j  z x a    1 ~ / ; G  S _ k w    o  6    " i8  i     a  H < ! &- P J D ] i ju    C  9  \ w  @`2 >\ h ,@ @  w  @   !(  4"= I#]   /551 1386324440 1009 1009 100664 31832 ` ELF>0B@@UHSHxH}HuHUHEH@@HEHEHEHE@ HHHHEHLHE@DHE@DHE@HE@HE@HE@DHE@HEHEHLT$ DL$DD$|$4$AEHƿHE@tGHEH0HEEEEEHEAAHƿHx[]]%CORES_C0Counts number of cores in C0CORES_C3Counts number of cores in C3CORES_C6Counts number of cores in C6@C0C3C6UNC_P_CLOCKTICKSPCU Uncore clockticksUNC_P_CORE0_TRANSITION_CYCLESCore C State Transition CyclesUNC_P_CORE1_TRANSITION_CYCLESUNC_P_CORE2_TRANSITION_CYCLESUNC_P_CORE3_TRANSITION_CYCLESUNC_P_CORE4_TRANSITION_CYCLESUNC_P_CORE5_TRANSITION_CYCLESUNC_P_CORE6_TRANSITION_CYCLESUNC_P_CORE7_TRANSITION_CYCLESUNC_P_DEMOTIONS_CORE0Core C State DemotionsUNC_P_DEMOTIONS_CORE1UNC_P_DEMOTIONS_CORE2UNC_P_DEMOTIONS_CORE3UNC_P_DEMOTIONS_CORE4UNC_P_DEMOTIONS_CORE5UNC_P_DEMOTIONS_CORE6UNC_P_DEMOTIONS_CORE7UNC_P_FREQ_BAND0_CYCLESFrequency ResidencyUNC_P_FREQ_BAND1_CYCLESUNC_P_FREQ_BAND2_CYCLESUNC_P_FREQ_BAND3_CYCLESUNC_P_FREQ_MAX_CURRENT_CYCLESCurrent Strongest Upper Limit CyclesUNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLESThermal Strongest Upper Limit CyclesUNC_P_FREQ_MAX_OS_CYCLESOS Strongest Upper Limit CyclesUNC_P_FREQ_MAX_POWER_CYCLESPower Strongest Upper Limit CyclesUNC_P_FREQ_MIN_IO_P_CYCLESIO P Limit Strongest Lower Limit CyclesUNC_P_FREQ_MIN_PERF_P_CYCLESPerf P Limit Strongest Lower Limit CyclesUNC_P_FREQ_TRANS_CYCLESCycles spent changing FrequencyUNC_P_MEMORY_PHASE_SHEDDING_CYCLESMemory Phase Shedding CyclesUNC_P_POWER_STATE_OCCUPANCYNumber of cores in C0UNC_P_PROCHOT_EXTERNAL_CYCLESExternal ProchotUNC_P_PROCHOT_INTERNAL_CYCLESInternal ProchotUNC_P_TOTAL_TRANSITION_CYCLESTotal Core C State Transition CyclesUNC_P_VOLT_TRANS_CYCLES_CHANGECycles Changing VoltageUNC_P_VOLT_TRANS_CYCLES_DECREASECycles Decreasing VoltageUNC_P_VOLT_TRANS_CYCLES_INCREASECycles Increasing VoltageUNC_P_VR_HOT_CYCLESVR Hot            ! " # $ %              /        2 [UNC_PCU=0x%lx event=0x%x occ_sel=0x%x en=%d inv=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s [UNC_PCU_FILTER=0x%lx band0=%u band1=%u band2=%u band3=%u] Intel Sandy Bridge-EP PCU uncoresnbep_unc_pcuuncore_pcuint^^B1 N W     ( 0 8 @  H !P "X $` &h (Wp ,Wt .ex 24 3I 4 8 Ap J K L M N PW R     WU{N{W8BC      !"#$%&'()*+,-./0123456789:;<=>?ίR~]12;3;@&r ' ( ) * + pmu,( -R,idx.W0 /W4 0W8<5@A;B;C;EFGHWIW@7p 8 9 : ; < =(idx>W, ?~0~48K5 6 7 89|@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ]!  ^' ( _7 ( `H!e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pes@ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]   ! {?p7 {G {aX "n c W Wt W W r ; W W WW W WW!  : {W4 4 G  ` P {"` 4 P ] v {W  v " 4   P *I + , - . / 0I ( 1;8 2;< 3;@ 4;D 5;HY { 6 @ = > ? @ A B; C;$ D;( E;, F;0 G;4 H 8 Y  Id  \# ]B8# ^B0# _B/# `B.# aB-# bB*# cB)# dB(# eB # fB  hT# iB8# jB0# kB/# lB.# mB-# nB,# oB*# pB)# qB(# rB # sB  u># vB8# wB2# xB0# yB/# zB.# {B-# |B,# }B*# ~B)# B(# B## B"# B!# B # B  # B8# B0# B/# B.# B-# B,# B+# B*# B)# B(# B # B  $tid B?$cid B<# B;# B8# B6$nid B.# B)$opc B # B# B  # B8# B0# B(# B # B  3# B:# B # B# B i$opc B:# B # B  Z%val [%com g%cbo t%pcu T%qpi >    3 i&%P'%(e%4 (val%)pe'PX)reg([P)f)@V Y q{*  a* . a {$* @ +E ,- % $ > $ > : ; I  I&I&  : ; : ;I8 : ;  : ;  : ; I8 I!I/ 'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8! : ; "'# : ; I 8 $ : ; I 8 % : ; I&.: ; '@B': ; I(: ; I)4: ; I*4: ; I+4: ; I?,!-4: ; I?<,Jw /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_intel_snbep_unc_pcu.ctypes.hstddef.hstdio.hlibio.hstdint.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hpfmlib_intel_snbep_unc_priv.hintel_snbep_unc_pcu_events.h %Kuf <v JwRxCyBzAN?q>H 1E@F?G>Hcntmskufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEsnbep_unc_p_occupancy_counters_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2unc_res1unc_res2unc_res3unc_res4unc_res5unc_res6statePFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFres0res1res2res3res4PFM_ATTR_CTRL_PERF_EVENTunc_umaskget_event_infoPFM_OS_NONEintel_snbep_unc_pcu_supportnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countunc_enPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXsnbep_unc_p_power_state_occupancypfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXunc_occctrlunc_occ_edgePFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000chardfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pnameunc_event_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERpcu_filtPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markerspfmlib_intel_snbep_unc_pcu.cPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tunc_invPFM_PMU_AMD64_FAM10H_SHANGHAIfilt0filt1filt2filt3uflagslong unsigned intmax_encodingha_addrpfm_snbep_unc_reg_t_flags2_IO_read_baseha_opcget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamedisplay_pcuPFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endPFM_PMU_INTEL_PPROumaskslo_addrnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOunc_event_extget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOunc_occ_invPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64unc_rstPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12unc_thresPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Isnbep_unc_modsosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetunc_tidPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intunc_edgedfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPintel_snbep_unc_p_pePFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regcbo_filtpfm_os_tsupported_plmpfmlib_event_desc_thi_addrGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx $JAC E@ .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @JHM`+ &M1; 6OpHCW$T)Qg+0b{0 {,v(| 0-00A-.A0A@@|pAG K<@_@ tJ   -Lipfmlib_intel_snbep_unc_pcu.csnbep_unc_p_power_state_occupancysnbep_unc_p_occupancy_countersintel_snbep_unc_p_pedisplay_pcu__pfm_vbprintfintel_snbep_unc_pcu_supportsnbep_unc_modspfm_intel_snbep_unc_detectpfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_snbep_unc_can_auto_encodepfm_intel_x86_get_event_attr_infopfm_intel_snbep_unc_get_encodingpfm_intel_snbep_unc_get_perf_encodingpfm_intel_snbep_unc_perf_validate_pattrspfm_intel_x86_validate_table 5 h?@HPhpx  &/ L(Up s/ v(Up  @ H      1 @ OH  m     @ H       @ .H  D  Z  p @ H     @0HX}8@@H`x$8@:HXi@H9Xy  A !J) 0 7 > > E L CS La f  q !~    + O      6   M#  0 1 = J @W d jq 8~   .          `  g  n  u ' | 4  A _ O V b n  z  z > .      w      ,  ?  #  ) /  5  ; A G M S Y _ e k q tw } h     k   ( ;   ) K   l        ' 6 E  T c   ] k  H % + 1 7 1= GC ]I sO U [ b  i  p w ~ N   [    ) j I c }  '  O k     H     & |- 4 ;  B I P W $^  e l  s z _ y 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" 1 @ ^ |            ($ K Z   c   D    v J Z r ~ K p L '  /581 1386324441 1009 1009 100664 37336 ` ELF>P@@UHHPH}HuHUHEH@@HEHEHEHE@ HHHHEHLHE@DHE@HE@HE@DHE@DHE@HEHEHLL$DD$|$4$EEHƿ^&_&FAILURE_CREDITSNumber of spawn failures due to lack of Egress creditsFAILURE_CREDITS_RBTNumber of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not setFAILURE_RBTNumber of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transactionSUCCESSNumber of spawn successesDRSNumber of times VN0 consumed for DRS message classHOMNumber of times VN0 consumed for HOM message classNCBNumber of times VN0 consumed for NCB message classNCSNumber of times VN0 consumed for NCS message classNDRNumber of times VN0 consumed for NDR message classSNPNumber of times VN0 consumed for SNP message class DATANumber of data flits over QPIIDLENumber of flits over QPI that do not hold protocol payloadNON_DATANumber of non-NULL non-data flits over QPINumber of flits over QPI on the Data Response (DRS) channelDRS_DATANumber of data flits over QPI on the Data Response (DRS) channelDRS_NONDATANumber of protocol flits over QPI on the Data Response (DRS) channelNumber of flits over QPI on the home channelHOM_NONREQNumber of non-request flits over QPI on the home channelHOM_REQNumber of data requests over QPI on the home channelNumber of snoop requests flits over QPINumber of non-coherent bypass flitsNCB_DATANumber of non-coherent data flitsNCB_NONDATANumber of bypass non-data flitsNumber of non-coherent standard (NCS) flitsNDR_ADNumber of flits received over Non-data response (NDR) channelNDR_AKNumber of flits received on the Non-data response (NDR) channel) UNC_Q_CLOCKTICKSNumber of qfclksUNC_Q_CTO_COUNTCount of CTO EventsUNC_Q_DIRECT2COREDirect 2 Core SpawningUNC_Q_L1_POWER_CYCLESCycles in L1UNC_Q_RXL0P_POWER_CYCLESCycles in L0pUNC_Q_RXL0_POWER_CYCLESCycles in L0UNC_Q_RXL_BYPASSEDRx Flit Buffer BypassedUNC_Q_RXL_CREDITS_CONSUMED_VN0VN0 Credit ConsumedUNC_Q_RXL_CREDITS_CONSUMED_VNAVNA Credit ConsumedUNC_Q_RXL_CYCLES_NERxQ Cycles Not EmptyUNC_Q_RXL_FLITS_G0Flits Received - Group 0UNC_Q_RXL_FLITS_G1Flits Received - Group 1UNC_Q_RXL_FLITS_G2Flits Received - Group 2UNC_Q_RXL_INSERTSRx Flit Buffer AllocationsUNC_Q_RXL_INSERTS_DRSRx Flit Buffer Allocations - DRSUNC_Q_RXL_INSERTS_HOMRx Flit Buffer Allocations - HOMUNC_Q_RXL_INSERTS_NCBRx Flit Buffer Allocations - NCBUNC_Q_RXL_INSERTS_NCSRx Flit Buffer Allocations - NCSUNC_Q_RXL_INSERTS_NDRRx Flit Buffer Allocations - NDRUNC_Q_RXL_INSERTS_SNPRx Flit Buffer Allocations - SNPUNC_Q_RXL_OCCUPANCYRxQ Occupancy - All PacketsUNC_Q_RXL_OCCUPANCY_DRSRxQ Occupancy - DRSUNC_Q_RXL_OCCUPANCY_HOMRxQ Occupancy - HOMUNC_Q_RXL_OCCUPANCY_NCBRxQ Occupancy - NCBUNC_Q_RXL_OCCUPANCY_NCSRxQ Occupancy - NCSUNC_Q_RXL_OCCUPANCY_NDRRxQ Occupancy - NDRUNC_Q_RXL_OCCUPANCY_SNPRxQ Occupancy - SNPUNC_Q_TXL0P_POWER_CYCLESUNC_Q_TXL0_POWER_CYCLESUNC_Q_TXL_BYPASSEDTx Flit Buffer BypassedUNC_Q_TXL_CYCLES_NETx Flit Buffer Cycles not EmptyUNC_Q_TXL_FLITS_G0Flits Transferred - Group 0UNC_Q_TXL_FLITS_G1Flits Transferred - Group 1UNC_Q_TXL_FLITS_G2Flits Transferred - Group 2UNC_Q_TXL_INSERTSTx Flit Buffer AllocationsUNC_Q_TXL_OCCUPANCYTx Flit Buffer OccupancyUNC_Q_VNA_CREDIT_RETURNSVNA Credits ReturnedUNC_Q_VNA_CREDIT_RETURN_OCCUPANCYVNA Credits Pending Return - Occupancy8                         [UNC_QPI=0x%lx event=0x%x sel_ext=%d umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel Sandy Bridge-EP QPI0 uncoresnbep_unc_qpi0uncore_qpi_0Intel Sandy Bridge-EP QPI1 uncoresnbep_unc_qpi1uncore_qpi_1int^^B1 N W     ( 0 8 @  H !P "X $` &h (Wp ,Wt .ex 24 3I 4 8 Ap J K L M N PW R     WU{N{W8BC      !"#$%&'()*+,-./0123456789:;<=>?ίR~]12;3;@&r ' ( ) * + pmu,( -R,idx.W0 /W4 0W8<5@A;B;C;EFGHWIW@7p 8 9 : ; < =(idx>W, ?~0~48K5 6 7 89|@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ]!  ^' ( _7 ( `H!e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pes@ uR H w] P x] X yn ` z] h { p | x } ~    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/usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_intel_snbep_unc_qpi.ctypes.hstddef.hstdio.hlibio.hstdint.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hpfmlib_intel_snbep_unc_priv.hintel_snbep_unc_qpi_events.h %= vf <wRxCyBzO}N?q>H ,cntmskufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2unc_res1unc_res2unc_res3unc_res4unc_res5unc_res6statePFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFres0res1res2res3res4PFM_ATTR_CTRL_PERF_EVENTunc_umaskget_event_infoPFM_OS_NONEdisplay_qpisnbep_unc_q_rxl_credits_consumed_vn0nattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countunc_enPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXunc_occctrlunc_occ_edgePFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000chardfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pnameunc_event_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERintel_snbep_unc_qpi1_supportpcu_filtPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTpfmlib_intel_snbep_unc_qpi.cPFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tunc_invPFM_PMU_AMD64_FAM10H_SHANGHAIfilt0filt1filt2filt3uflagslong unsigned intmax_encodingha_addrsnbep_unc_q_rxl_flits_g0snbep_unc_q_rxl_flits_g1snbep_unc_q_rxl_flits_g2pfm_snbep_unc_reg_t_flags2_IO_read_baseha_opcget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTintel_snbep_unc_q_peudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endPFM_PMU_INTEL_PPROumaskslo_addrnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOunc_event_extget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOunc_occ_invPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMcan_auto_encodeget_event_attr_infosizelong long unsigned intintel_snbep_unc_qpi0_supportPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64unc_rstPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12unc_thresPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Isnbep_unc_modsosidsnbep_unc_q_direct2corePFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetunc_tidPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intunc_edgedfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regcbo_filtpfm_os_tsupported_plmpfmlib_event_desc_thi_addrGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx AC  .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @8\0+  &h\1 ;  6_ H#Cl$T7Qg90bx0 {:v 0;0mO-OO8OXV` Y}@6 [t` 0     ;XuC`pfmlib_intel_snbep_unc_qpi.csnbep_unc_q_direct2coresnbep_unc_q_rxl_credits_consumed_vn0snbep_unc_q_rxl_flits_g0snbep_unc_q_rxl_flits_g1snbep_unc_q_rxl_flits_g2intel_snbep_unc_q_pedisplay_qpi__pfm_vbprintfintel_snbep_unc_qpi0_supportsnbep_unc_modspfm_intel_snbep_unc_detectpfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_get_event_attr_infopfm_intel_snbep_unc_get_encodingpfm_intel_snbep_unc_get_perf_encodingpfm_intel_snbep_unc_perf_validate_pattrspfm_intel_x86_validate_tableintel_snbep_unc_qpi1_support  x@HPhpx  !!"@HPhpx  !!"G` (pTx\ (px38kp`h#(@cHp` h     (P X p    @ H ( 3  0  8    k  < (H p x  (X`/hERky (`h ';O d(wX`h`   (0`Qhh (`1hHi} (`h 5Ia u(`hk (`8hKgz`  (`h8Px  l  !) 0 7 > f E L S a f  q f~    S     |  U  w #  0 Y = J !W d Kq )~  f M     C           '  4 > A ~ O V b `n  z   > b     \ X 2    H T  s  M#  ) /  5  ; wA sG 1M S Y _ e k <q Hw }     f ?     z f n s  s ]      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K W  c o  { j  {  * :   S   MH y          % 1 ~=  Z  m y ,   p  v * i  -   . =  L [ j y          R   ' 6 E ] l { .           d  ;/ G V e t           " 1 @ ^ |         4  $ K Z  Y T  c  9  - y c o 9    `    %  1? j KT 7`#t   /611 1386324441 1009 1009 100664 20928 ` ELF>(@@`DOORBELL_RCVDTBDINT_PRIOIPI_RCVDMSI_RCVDVLW_RCVDUNC_U_EVENT_MSGVLW ReceivedUNC_U_LOCK_CYCLESIDI Lock/SplitLock CyclesBDIntel Sandy Bridge-EP U-Box uncoresnbep_unc_ubouncore_uboxxintNNz2z1 > G t t t t t( t0 t8 t@  tH !tP "tX $v` &|h (Gp ,Gt .Ux 2$ 39 4 8 A` Jr Kr Lr Mr N PG R  v v | GEzk>zkGr82C      !"#$%&'()*+,-./0123456789:;<=>?ΟB nMy12+3+@&b ' ( ) * + pmu,( -B,idx.G0 /G4 0G8<5@A+B+C+EFGHGIG@7` 8 9 : ; < =(idx>G, ?n0n48K5 6 7 89l@ABt>id?GDPS pmuT UG VG WG XG Y ZG [ ]  ^ ( _' ( `rH!e f g hpmui jG kG lG$ mG( nG, oG0 pG4 r8pes@ uB H wM P xM X y^ ` zM h {x p | x } ~x    0 V  M    k?`z' k7 kaH "^ rS Gx rGd G rG b~ + rG G rGG G rGG  *  kG$ r$ 7  P @ k"P r$ @ M f kGz rz f " r$ r  P*9 + , - . / 09 ( 1+8 2+< 3+@ 4+D 5+HI k6 @= > ? @ A B+ C+$ D+( E+, F+0 G+4 H 8 I IT I k#    1k# 8F !$ $ k%& v`% $ > $ > : ; I  I&I&  : ; : ;I8 : ;  : ;  : ; I8 I!I/ 'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8! : ; "'#4: ; I$4: ; I?%!&4: ; I?<}w /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventstypes.hstddef.hstdio.hlibio.hstdint.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hintel_snbep_unc_ubo_events.hpfmlib_intel_snbep_unc_ubo.cpfmlib_intel_snbep_unc_priv.hcntmskufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000chardfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encoding_flags2_IO_read_baseget_event_next_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodeintel_snbep_unc_u_pePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endPFM_PMU_INTEL_PPROumasksintel_snbep_unc_ubo_supportnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64snbep_unc_modsPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Iosidsnbep_unc_u_event_msgPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfmlib_intel_snbep_unc_ubo.cpfm_attr_treserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2).symtab.strtab.shstrtab.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.debug_line.debug_str.comment.note.GNU-stack@&@ !1,@6@ 13hC|>4Obj ]Q q}0 0'-((h- 0@4     Iet#Efpfmlib_intel_snbep_unc_ubo.csnbep_unc_u_event_msgintel_snbep_unc_u_peintel_snbep_unc_ubo_supportsnbep_unc_modspfm_intel_snbep_unc_detectpfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_get_event_attr_infopfm_intel_snbep_unc_get_encodingpfm_intel_snbep_unc_get_perf_encodingpfm_intel_snbep_unc_perf_validate_pattrspfm_intel_x86_validate_table@ HPhpx@H0$8- (X@`h   V S' . 5 < C Q )V 3 a n }    4  o  w   - C: G a T Ka Mn _{    w  q    -  4  ;  B  I $ 1 ? ;F YR ^ P j  1 >  ;  M  X  ;         % 3 + 1 77 = MC ^I O HU [ a g m s Xy f c D F Y         t   M   . = & L [       & d! z' - 3 9 ? E K R Y ` g n u T |  ~        -  G  d {            0 H $ + a 2 9 @ G aN U y\ c j q )x O i j 2   !  E     0 x  l  V / q   R $ f* 30 6 < 'C lV \ sb h o   , o d  V  : 6    ( B O c 5x  V  :     6    - G a wu 6   "       " . : F R  _  l @y =  6 >    C w  / ; &G K S E_ Fk w  Y   h 8   5 > F \     :! - J ] 6i u   |  "  @2 > L Xl b  /641 1386324441 1009 1009 100664 24424 ` ELF>`1@@a CCW_EVENCounter-clockwise and even ring polarityCCW_ODDCounter-clockwise and odd ring polarityCW_EVENClockwise and even ring polarityCW_ODDClockwise and odd ring polarityCW_ANYClockwise with any polarityCCW_ANYCounter-clockwise with any polarityANYany direction and any polarity  R2 IV Ring in Use DRSDRS Ingress queueNCBNCB Ingress queueNCSNCS Ingress queue ADAD Egress queueAKAK Egress queueBLBL Egress queueUNC_R2_CLOCKTICKSNumber of uclks in domainUNC_R2_RING_AD_USEDR2 AD Ring in UseUNC_R2_RING_AK_USEDR2 AK Ring in UseUNC_R2_RING_BL_USEDR2 BL Ring in UseUNC_R2_RING_IV_USEDUNC_R2_RXR_AK_BOUNCESAK Ingress BouncedUNC_R2_RXR_CYCLES_NEIngress Cycles Not EmptyUNC_R2_TXR_CYCLES_FULLEgress Cycles FullUNC_R2_TXR_CYCLES_NEEgress Cycles Not EmptyUNC_R2_TXR_INSERTSEgress allocations  %#$Intel Sandy Bridge-EP R2PCIe uncoresnbep_unc_r2pcieuncore_r2pcieintNNz2z1 > G t t t t t( t0 t8 t@  tH !tP "tX $v` &|h (Gp ,Gt .Ux 2$ 39 4 8 A` Jr Kr Lr Mr N PG R  v v | GEzk>zkGr82C      !"#$%&'()*+,-./0123456789:;<=>?ΟB nMy12+3+@&b ' ( ) * + pmu,( -B,idx.G0 /G4 0G8<5@A+B+C+EFGHGIG@7` 8 9 : ; < =(idx>G, ?n0n48K5 6 7 89l@ABt>id?GDPS pmuT UG VG WG XG Y ZG [ ]  ^ ( _' ( `rH!e f g hpmui jG kG lG$ mG( nG, oG0 pG4 r8pes@ uB H wM P xM X y^ ` zM h {x p | x } ~x    0 V  M    k?`z' k7 kaH "^ rS Gx rGd G rG b~ + rG G rGG G rGG  *  kG$ r$ 7  P @ k"P r$ @ M f kGz rz f " r$ r  P*9 + , - . / 09 ( 1+8 2+< 3+@ 4+D 5+HI k6 @= > ? @ A B+ C+$ D+( E+, F+0 G+4 H 8 I IT I k#   I 1k# >F !I [k# Fp K# X K k # j $ $ %& % $ > $ > : ; I  I&I&  : ; : ;I8 : ;  : ;  : ; I8 I!I/ 'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8! : ; "'#4: ; I$4: ; I?%!&4: ; I?<} /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventstypes.hstddef.hstdio.hlibio.hstdint.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hintel_snbep_unc_r2pcie_events.hpfmlib_intel_snbep_unc_r2pcie.cpfmlib_intel_snbep_unc_priv.hcntmskufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kpfmlib_intel_snbep_unc_r2pcie.c_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmsksnbep_unc_r2_rxr_cycles_nePFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminatesnbep_unc_r2_ring_iv_usedunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000chardfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encoding_flags2_IO_read_baseget_event_next_unused2intel_snbep_unc_r2pcie_supportPFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endPFM_PMU_INTEL_PPROumasksnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3snbep_unc_r2_txr_cycles_full__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64snbep_unc_modsPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Isnbep_unc_r2_ring_ad_usedosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUintel_snbep_unc_r2_pePFM_OS_MAX_IO_read_endmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2).symtab.strtab.shstrtab.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.debug_line.debug_str.comment.note.GNU-stack@&@ !8;,@6@ 1<(C >B@Ob ]P_ q}0e*00-00 6 9/!@0;PU@p     'Dcpfmlib_intel_snbep_unc_r2pcie.csnbep_unc_r2_ring_ad_usedsnbep_unc_r2_ring_iv_usedsnbep_unc_r2_rxr_cycles_nesnbep_unc_r2_txr_cycles_fullintel_snbep_unc_r2_peintel_snbep_unc_r2pcie_supportsnbep_unc_modspfm_intel_snbep_unc_detectpfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_get_event_attr_infopfm_intel_snbep_unc_get_encodingpfm_intel_snbep_unc_get_perf_encodingpfm_intel_snbep_unc_perf_validate_pattrspfm_intel_x86_validate_table   @HPhpx@H9Hpx08 (p@H  03CF V(Yp@Hx@@@  p8 @ "H 8 K ` @ y    8 @ H   Y   ' ;. N 5  < C gQ )V  a 1n } B  > s  o    G w m   A - : G  T Ka n _{  ?  w               $ 5 1 d? F yR +^  j   > R     1  X "     K  c       %  + &1 77 = MC I O HU [ a g .m s y f       C  [  !      m 2  t   {    x  ~  [  & ! ' - 3 9 ? OE K R  Y  ` g n u  | {       Y  s             7 S [ . K h   $ %+  2 9 $@ CG N  U \  c j oq x    2 $      W    0  l     v   V  $ f* 0 6 U < GC V  \ b h o ;              9  ;( @B O c Ux *       2  N     9  ;- G a u        M   G ;  $ " . Q: , F R e _ q l y x v    > 2  e    / q; G  S _ k Uw  F   %   C V  8  n   f |      ! -  J  ] i  u   ;     B  b 7@2 >\ h@v p   m   /674 1386324441 1009 1009 100664 28664 ` ELF>;@@bcDRSNCBNCS CCW_EVENCounter-Clockwise and even ring polarityCCW_ODDCounter-Clockwise and odd ring polarityCW_EVENClockwise and even ring polarityCW_ODDClockwise and odd ring polarityANYAny polarity ADIngress Bypassed DRS Ingress queueHOMHOM Ingress queueNCB Ingress queueNCS Ingress queueNDRNDR Ingress queueSNPSNP Ingress queue Filter DRS message classFilter HOM message classFilter NCB message classFilter NCS message classFilter NDR message classFilter SNP message class UNC_R3_CLOCKTICKSNumber of uclks in domainUNC_R3_IIO_CREDITS_ACQUIREDto IIO BL Credit AcquiredUNC_R3_IIO_CREDITS_REJECTto IIO BL Credit RejectedUNC_R3_IIO_CREDITS_USEDto IIO BL Credit In UseUNC_R3_RING_AD_USEDR3 AD Ring in UseUNC_R3_RING_AK_USEDR3 AK Ring in UseUNC_R3_RING_BL_USEDR3 BL Ring in UseUNC_R3_RING_IV_USEDR3 IV Ring in UseUNC_R3_RXR_BYPASSEDUNC_R3_RXR_CYCLES_NEIngress Cycles Not EmptyUNC_R3_RXR_INSERTSIngress AllocationsUNC_R3_RXR_OCCUPANCYIngress Occupancy AccumulatorUNC_R3_TXR_CYCLES_FULLEgress cycles fullUNC_R3_TXR_INSERTSEgress allocationsUNC_R3_TXR_NACKEgress NackUNC_R3_VN0_CREDITS_REJECTVN0 Credit Acquisition Failed on DRSUNC_R3_VN0_CREDITS_USEDVN0 Credit UsedUNC_R3_VNA_CREDITS_ACQUIREDVNA credit AcquisitionsUNC_R3_VNA_CREDITS_REJECTVNA Credit RejectUNC_R3_VNA_CREDIT_CYCLES_OUTCycles with no VNA credits availableUNC_R3_VNA_CREDIT_CYCLES_USEDCycles with 1 or more VNA credits in use !"  %$&763412Intel Sandy Bridge-EP R3QPI0 uncoresnbep_unc_r3qpi0uncore_r3qpi_0Intel Sandy Bridge-EP R3QPI1 uncoresnbep_unc_r3qpi1uncore_r3qpi_1?intNNz2z1 > G t t t t t( t0 t8 t@  tH !tP "tX $v` &|h (Gp ,Gt .Ux 2$ 39 4 8 A` Jr Kr Lr Mr N PG R  v v | GEzk>zkGr82C      !"#$%&'()*+,-./0123456789:;<=>?ΟB nMy12+3+@&b ' ( ) * + pmu,( -B,idx.G0 /G4 0G8<5@A+B+C+EFGHGIG@7` 8 9 : ; < =(idx>G, ?n0n48K5 6 7 89l@ABt>id?GDPS pmuT UG VG WG XG Y ZG [ ]  ^ ( _' ( `rH!e f g hpmui jG kG lG$ mG( nG, oG0 pG4 r8pes@ uB H wM P xM X y^ ` zM h {x p | x } ~x    0 V  M    k?`z' k7 kaH "^ rS Gx rGd G rG b~ + rG G rGG G rGG  *  kG$ r$ 7  P @ k"P r$ @ M f kGz rz f " r$ r  P*9 + , - . / 09 ( 1+8 2+< 3+@ 4+D 5+HI k6 @= > ? @ A B+ C+$ D+( E+, F+0 G+4 H 8 I IT I k#   I 1k# 0F !I [k# Gp K# O KI k# W # x  k#  $ ? $ @ 2%& ='% $ > $ > : ; I  I&I&  : ; : ;I8 : ;  : ;  : ; I8 I!I/ 'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8! : ; "'#4: ; I$4: ; I?%!&4: ; I?<{ /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventstypes.hstddef.hstdio.hlibio.hstdint.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hintel_snbep_unc_r3qpi_events.hpfmlib_intel_snbep_unc_r3qpi.cpfmlib_intel_snbep_unc_priv.hcntmskufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tsnbep_unc_r3_rxr_bypasseduequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlsnbep_unc_r3_iio_credits_acquiredPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000chardfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tmodmsk_reqdfl_val64modhwPFM_DTYPE_RATIOumodelintel_snbep_unc_r3_penumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1intel_x86_entry_tPFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176snbep_unc_r3_rxr_cycles_nePFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encoding_flags2_IO_read_baseget_event_next_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_t_IO_write_endPFM_PMU_INTEL_PPROumasksintel_snbep_unc_r3qpi1_supportnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3snbep_unc_r3_ring_ad_used__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64snbep_unc_modsPFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3snbep_unc_r3_vn0_credits_reject_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodepfmlib_intel_snbep_unc_r3qpi.cdtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedintel_snbep_unc_r3qpi0_supportPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tsnbep_unc_r3_ring_iv_usedGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2).symtab.strtab.shstrtab.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.debug_line.debug_str.comment.note.GNU-stack@&@ !E`,@6@ 1H0 CC>RO/$b& ]o q &}0'0,:-Y:Y:?0 B  B@\@PvP  @    *He'Pmpfmlib_intel_snbep_unc_r3qpi.csnbep_unc_r3_iio_credits_acquiredsnbep_unc_r3_ring_ad_usedsnbep_unc_r3_ring_iv_usedsnbep_unc_r3_rxr_bypassedsnbep_unc_r3_rxr_cycles_nesnbep_unc_r3_vn0_credits_rejectintel_snbep_unc_r3_peintel_snbep_unc_r3qpi0_supportsnbep_unc_modspfm_intel_snbep_unc_detectpfm_intel_x86_get_event_firstpfm_intel_x86_get_event_nextpfm_intel_x86_get_event_infopfm_intel_x86_get_event_nattrspfm_intel_x86_event_is_validpfm_intel_x86_get_event_attr_infopfm_intel_snbep_unc_get_encodingpfm_intel_snbep_unc_get_perf_encodingpfm_intel_snbep_unc_perf_validate_pattrspfm_intel_x86_validate_tableintel_snbep_unc_r3qpi1_support DU@ HPhpx h@ HPhpx (px 0I8X@ H$"&@H8J\`0r8v (p"x`\hr   , ( H X  ` b h |         ( X` h& 8 L @^  r ( X` h     $ (7 `J hZ f        ( ` h  - P u    ? u   m' ~. f 5 8< C Q )V  a fn } )  S l  N !   _ w    Y - : G  T Ka n _{ 9 W  w              $ J 1 |? wF YR `^  j   > K     F  X     J `  \  M     %  + i1 77 = MC I O HU [ %a g m s y f       X  s  u      g +  q   b        p  & d! z' - 3 9 ? 6E K R  Y  ` g -n u  |    1   n        ~       2   2 O l  $ +  2 9 !@ @G {N 4 U \  c cj q x    2            0     7       $ f* 0 6 j < 'C V  \ b h o P      B    r ,  N  p( B O Ac 5x ?       J   r ,  N  p- G a u r ,  z   F   . S  < " . : D F R z _  l y W  , r 5 > J     K / ; G  S __ k mw    * :   <   68 Y U   ` v   1  ! - ( J  ] ri ,u   p     "  _  2  >\ mh@v F       J   !3   /706 1386324441 1009 1009 100664 35456 ` ELF>PU@@UHH H}E}tE* ttd; BANK_CONFLICTSNumber of actual bank conflictsBRANCHESNumber of taken and not taken branches, including: conditional branches, jumps, calls, returns, software interrupts, and interrupt returnsBRANCHES_MISPREDICTEDNumber of branch mispredictions that occurred on BTB hits. BTB misses are not considered branch mispredicts because no prediction exists for them yet.CODE_CACHE_MISSNumber of instruction reads that miss the internal code cache; whether the read is cacheable or noncacheableCODE_PAGE_WALKNumber of code page walksCODE_READNumber of instruction reads; whether the read is cacheable or noncacheableCPU_CLK_UNHALTEDNumber of cycles during which the processor is not halted.DATA_CACHE_LINES_WRITTEN_BACKNumber of dirty lines (all) that are written back, regardless of the causeDATA_PAGE_WALKNumber of data page walksDATA_READNumber of successful memory data reads committed by the K-unit (L1). Cache accesses resulting from prefetch instructions are included for A0 stepping.DATA_READ_MISSNumber of memory read accesses that miss the internal data cache whether or not the access is cacheable or noncacheable. Cache accesses resulting from prefetch instructions are not included.DATA_READ_MISS_OR_WRITE_MISSNumber of memory read and/or write accesses that miss the internal data cache, whether or not the access is cacheable or noncacheableDATA_READ_OR_WRITENumber of memory data reads and/or writes (internal data cache hit and miss combined). Read cache accesses resulting from prefetch instructions are included for A0 stepping.DATA_WRITENumber of successful memory data writes committed by the K-unit (L1). Streaming stores (hit/miss L1), cacheable write partials, and UC promotions are all included.DATA_WRITE_MISSNumber of memory write accesses that miss the internal data cache whether or not the access is cacheable. Non-cacheable misses are not included.EXEC_STAGE_CYCLESNumber of E-stage cycles that were successfully completed. Includes cycles generated by multi-cycle E-stage instructions. For instructions destined for the FPU or VPU pipelines, this event only counts occupancy in the integer E-stage.FE_STALLEDNumber of cycles where the front-end could not advance. Any multi-cycle instructions which delay pipeline advance and apply backpressure to the front-end will be included, e.g. read-modify-write instructions. Includes cycles when the front-end did not have any instructions to issue.INSTRUCTIONS_EXECUTEDNumber of instructions executed (up to two per clock)INSTRUCTIONS_EXECUTED_V_PIPENumber of instructions executed in the V_pipe. The event indicates the number of instructions that were paired.L1_DATA_HIT_INFLIGHT_PF1Number of data requests which hit an in-flight vprefetch0. The in-flight vprefetch0 was not necessarily issued from the same thread as the data request.L1_DATA_PF1Number of data vprefetch0 requests seen by the L1.L1_DATA_PF1_DROPNumber of data vprefetch0 requests seen by the L1 which were dropped for any reason. A vprefetch0 can be dropped if the requested address matches another in-flight request or if it has a UC memtype.L1_DATA_PF1_MISSNumber of data vprefetch0 requests seen by the L1 which missed L1. Does not include vprefetch1 requests which are counted in L1_DATA_PF1_DROP.L1_DATA_PF2Number of data vprefetch1 requests seen by the L1. This is not necessarily the same number as seen by the L2 because this count includes requests that are dropped by the core. A vprefetch1 can be dropped by the core if the requested address matches another in-flight request or if it has a UC memtype.L2_CODE_READ_MISS_CACHE_FILLNumber of code read accesses that missed the L2 cache and were satisfied by another L2 cache. Can include promoted read misses that started as DATA accesses.L2_CODE_READ_MISS_MEM_FILLNumber of code read accesses that missed the L2 cache and were satisfied by main memory. Can include promoted read misses that started as DATA accesses.L2_DATA_HIT_INFLIGHT_PF2Number of data requests which hit an in-flight vprefetch1. The in-flight vprefetch1 was not necessarily issued from the same thread as the data request.L2_DATA_PF1_MISSNumber of data vprefetch0 requests seen by the L2 which missed L2.L2_DATA_PF2Number of data vprefetch1 requests seen by the L2. Only counts vprefetch1 hits on A0 stepping.L2_DATA_PF2_DROPNumber of data vprefetch1 requests seen by the L2 which were dropped for any reason.L2_DATA_PF2_MISSNumber of data vprefetch1 requests seen by the L2 which missed L2. Does not include vprefetch2 requests which are counted in L2_DATA_PF2_DROP.L2_DATA_READ_MISS_CACHE_FILLNumber of data read accesses that missed the L2 cache and were satisfied by another L2 cache. Can include promoted read misses that started as CODE accesses.L2_DATA_READ_MISS_MEM_FILLNumber of data read accesses that missed the L2 cache and were satisfied by main memory. Can include promoted read misses that started as CODE accesses.L2_DATA_WRITE_MISS_CACHE_FILLNumber of data write (RFO) accesses that missed the L2 cache and were satisfied by another L2 cache.L2_DATA_WRITE_MISS_MEM_FILLNumber of data write (RFO) accesses that missed the L2 cache and were satisfied by main memory.L2_READ_HIT_EL2 Read Hit E State, may include prefetches on A0 stepping.L2_READ_HIT_ML2 Read Hit M StateL2_READ_HIT_SL2 Read Hit S StateL2_READ_MISSL2 Read Misses. Prefetch and demand requests to the same address will produce double counting.L2_VICTIM_REQ_WITH_DATAL2 received a victim request and responded with dataL2_WRITE_HITL2 Write HIT, may undercount on A0 stepping.LONG_CODE_PAGE_WALKNumber of long code page walks, i.e. page walks that also missed the L2 uTLB. Subset of DATA_CODE_WALK eventLONG_DATA_PAGE_WALKNumber of long data page walks, i.e. page walks that also missed the L2 uTLB. Subset of DATA_PAGE_WALK eventMEMORY_ACCESSES_IN_BOTH_PIPESNumber of data memory reads or writes that are paired in both pipes of the pipelineMICROCODE_CYCLESThe number of cycles microcode is executing. While microcode is executing, all other threads are stalled.PIPELINE_AGI_STALLSNumber of address generation interlock (AGI) stalls. An AGI occurring in both the U- and V- pipelines in the same clock signals this event twice.PIPELINE_FLUSHESNumber of pipeline flushes that occur. Pipeline flushes are caused by BTB misses on taken branches, mispredictions, exceptions, interrupts, and some segment descriptor loads.PIPELINE_SG_AGI_STALLSNumber of address generation interlock (AGI) stalls due to vscatter* and vgather* instructions.SNP_HITM_BUNITSnoop HITM in BUNITSNP_HITM_L2Snoop HITM in L2SNP_HIT_L2Snoop HIT in L2VPU_DATA_READNumber of read transactions that were issued. In general each read transaction will read 1 64B cacheline. If there are alignment issues, then reads against multiple cache lines will each be counted individually.VPU_DATA_READ_MISSVPU L1 data cache readmiss. Counts the number of occurrences.VPU_DATA_WRITENumber of write transactions that were issued. . In general each write transaction will write 1 64B cacheline. If there are alignment issues, then write against multiple cache lines will each be counted individually.VPU_DATA_WRITE_MISSVPU L1 data cache write miss. Counts the number of occurrences.VPU_ELEMENTS_ACTIVECounts the cumulative number of elements active (via mask) for VPU instructions issued.VPU_INSTRUCTIONS_EXECUTEDCounts the number of VPU instructions executed in both u- and v-pipes.VPU_INSTRUCTIONS_EXECUTED_V_PIPECounts the number of VPU instructions that paired and executed in the v-pipe.VPU_STALL_REGVPU stall on Register Dependency. Counts the number of occurrences. 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/usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_intel_knc.ctypes.hstddef.hstdint.hstdio.hlibio.hpfmlib.hpfmlib_priv.hpfmlib_intel_x86_priv.hintel_knc_events.h gZvr$Ycntmskpfm_intel_x86_cfgufilterssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64PFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2intel_knc_pePFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intintel_knc_supportPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kintel_x86_mods_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tuequivPFM_PMU_PPC970ucntmskPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned 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intmax_encoding_flags2_IO_read_baseget_event_nextthis_unused2PFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1intel_x86_umask_tpfm_knc_detect_IO_write_endPFM_PMU_INTEL_PPROumasksnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsumodmsk_reqPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstrpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMsteppingcan_auto_encodeget_event_attr_infosizelong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsarch_versionPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endpfm_intel_x86_config_tmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24Kpfmlib_intel_knc.cPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx KAC F .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @K_H+ &_1;- 6pa H/ClT> g@0b 0 {@ivP 0.B0)T-VTXT8hT[ ] !K   0EWix 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TC_deliver_modeThe duration (in clock cycles) of the operating modes of the trace cache and decode engine in the processor packageDDBoth logical CPUs in deliver modeDBLogical CPU 0 in deliver mode and logical CPU 1 in build modeDILogical CPU 0 in deliver mode and logical CPU 1 either halted, under machine clear condition, or transitioning to a long microcode flowBDLogical CPU 0 in build mode and logical CPU 1 is in deliver modeBBBoth logical CPUs in build modeBILogical CPU 0 in build mode and logical CPU 1 either halted, under machine clear condition, or transitioning to a long microcode flowIDLogical CPU 0 either halted, under machine clear condition, or transitioning to a long microcode flow, and logical CPU 1 in deliver modeIBLogical CPU 0 either halted, under machine clear condition, or transitioning to a long microcode flow, and logical CPU 1 in build modeBPU_fetch_requestInstruction fetch requests by the Branch Prediction UnitTCMISSTrace cache lookup missITLB_referenceTranslations using the Instruction Translation Look-Aside BufferHITITLB hitMISSITLB missHIT_UCUncacheable ITLB hitmemory_cancelCanceling of various types of requests in the Data cache Address Control unit (DAC)ST_RB_FULLReplayed because no store request buffer is available64K_CONFConflicts due to 64K aliasingmemory_completeCompletions of a load split, store split, uncacheable (UC) split, or UC loadLSCLoad split completed, excluding UC/WC loadsSSCAny split stores completedload_port_replayReplayed events at the load portSPLIT_LDSplit loadstore_port_replayReplayed events at the store portSPLIT_STSplit storeMOB_load_replayCount of times the memory order buffer (MOB) caused a load operation to be replayedNO_STAReplayed because of unknown store addressNO_STDReplayed because of unknown store dataPARTIAL_DATAReplayed because of partially overlapped data access between the load and store operationsUNALGN_ADDRReplayed because the lower 4 bits of the linear address do not match between the load and store operationspage_walk_typePage walks that the page miss handler (PMH) performsDTMISSPage walk for a data TLB miss (load or store)ITMISSPage walk for an instruction TLB missBSQ_cache_referenceCache references (2nd or 3rd level caches) as seen by the bus unit. Read types include both load and RFO, and write types include writebacks and evictionsRD_2ndL_HITSRead 2nd level cache hit SharedRD_2ndL_HITERead 2nd level cache hit ExclusiveRD_2ndL_HITMRead 2nd level cache hit ModifiedRD_3rdL_HITSRead 3rd level cache hit SharedRD_3rdL_HITERead 3rd level cache hit ExclusiveRD_3rdL_HITMRead 3rd level cache hit ModifiedRD_2ndL_MISSRead 2nd level cache missRD_3rdL_MISSRead 3rd level cache missWR_2ndL_MISSA writeback lookup from DAC misses the 2nd level cache (unlikely to happen)IOQ_allocationCount of various types of transactions on the bus. A count is generated each time a transaction is allocated into the IOQ that matches the specified mask bits. An allocated entry can be a sector (64 bytes) or a chunk of 8 bytes. Requests are counted once per retry. All 'TYPE_BIT*' event-masks together are treated as a single 5-bit valueTYPE_BIT0Bus request type (bit 0)TYPE_BIT1Bus request type (bit 1)TYPE_BIT2Bus request type (bit 2)TYPE_BIT3Bus request type (bit 3)TYPE_BIT4Bus request type (bit 4)ALL_READCount read entriesALL_WRITECount write entriesMEM_UCCount UC memory access entriesMEM_WCCount WC memory access entriesMEM_WTCount write-through (WT) memory access entriesMEM_WPCount write-protected (WP) memory access entriesMEM_WBCount WB memory access entriesOWNCount all store requests driven by processor, as opposed to other processor or DMAOTHERCount all requests driven by other processors or DMAPREFETCHInclude HW and SW prefetch requests in the countIOQ_active_entriesNumber of entries (clipped at 15) in the IOQ that are active. An allocated entry can be a sector (64 bytes) or a chunk of 8 bytes. This event must be programmed in conjuction with IOQ_allocation. All 'TYPE_BIT*' event-masks together are treated as a single 5-bit valueFSB_data_activityCount of DRDY or DBSY events that occur on the front side busDRDY_DRVCount when this processor drives data onto the bus. Includes writes and implicit writebacksDRDY_OWNCount when this processor reads data from the bus. Includes loads and some PIC transactions. Count DRDY events that we drive. Count DRDY events sampled that we ownDRDY_OTHERCount when data is on the bus but not being sampled by the processor. It may or may not be driven by this processorDBSY_DRVCount when this processor reserves the bus for use in the next bus cycle in order to drive dataDBSY_OWNCount when some agent reserves the bus for use in the next bus cycle to drive data that this processor will sampleDBSY_OTHERCount when some agent reserves the bus for use in the next bus cycle to drive data that this processor will NOT sample. It may or may not be being driven by this processorBSQ_allocationAllocations in the Bus Sequence Unit (BSQ). The event mask bits consist of four sub-groups: request type, request length, memory type, and a sub-group consisting mostly of independent bits (5 through 10). Must specify a mask for each sub-groupREQ_TYPE0Along with REQ_TYPE1, request type encodings are: 0 - Read (excludes read invalidate), 1 - Read invalidate, 2 - Write (other than writebacks), 3 - Writeback (evicted from cache)REQ_TYPE1Along with REQ_TYPE0, request type encodings are: 0 - Read (excludes read invalidate), 1 - Read invalidate, 2 - Write (other than writebacks), 3 - Writeback (evicted from cache)REQ_LEN0Along with REQ_LEN1, request length encodings are: 0 - zero chunks, 1 - one chunk, 3 - eight chunksREQ_LEN1Along with REQ_LEN0, request length encodings are: 0 - zero chunks, 1 - one chunk, 3 - eight chunksREQ_IO_TYPERequest type is input or outputREQ_LOCK_TYPERequest type is bus lockREQ_CACHE_TYPERequest type is cacheableREQ_SPLIT_TYPERequest type is a bus 8-byte chunk split across an 8-byte boundaryREQ_DEM_TYPE0: Request type is HW.SW prefetch. 1: Request type is a demandREQ_ORD_TYPERequest is an ordered typeMEM_TYPE0Along with MEM_TYPE1 and MEM_TYPE2, memory type encodings are: 0 - UC, 1 - USWC, 4- WT, 5 - WP, 6 - WBMEM_TYPE1Along with MEM_TYPE0 and MEM_TYPE2, memory type encodings are: 0 - UC, 1 - USWC, 4- WT, 5 - WP, 6 - WBMEM_TYPE2Along with MEM_TYPE0 and MEM_TYPE1, memory type encodings are: 0 - UC, 1 - USWC, 4- WT, 5 - WP, 6 - WBBSQ_active_entriesNumber of BSQ entries (clipped at 15) currently active (valid) which meet the subevent mask criteria during allocation in the BSQ. Active request entries are allocated on the BSQ until de-allocated. De-allocation of an entry does not necessarily imply the request is filled. This event must be programmed in conjunction with BSQ_allocationSSE_input_assistNumber of times an assist is requested to handle problems with input operands for SSE/SSE2/SSE3 operations; most notably denormal source operands when the DAZ bit isn't setALLCount assists for SSE/SSE2/SSE3 uopspacked_SP_uopNumber of packed single-precision uopsCount all uops operating on packed single-precisions operandsTAG0Tag this event with tag bit 0 for retirement counting with execution_eventTAG1Tag this event with tag bit 1 for retirement counting with execution_eventTAG2Tag this event with tag bit 2 for retirement counting with execution_eventTAG3Tag this event with tag bit 3 for retirement counting with execution_eventpacked_DP_uopNumber of packed double-precision uopsCount all uops operating on packed double-precisions operandsscalar_SP_uopNumber of scalar single-precision uopsCount all uops operating on scalar single-precisions operandsscalar_DP_uopNumber of scalar double-precision uopsCount all uops operating on scalar double-precisions operands64bit_MMX_uopNumber of MMX instructions which operate on 64-bit SIMD operandsCount all uops operating on 64-bit SIMD integer operands in memory or MMX registers128bit_MMX_uopNumber of MMX instructions which operate on 128-bit SIMD operandsCount all uops operating on 128-bit SIMD integer operands in memory or MMX registersx87_FP_uopNumber of x87 floating-point uopsCount all x87 FP uopsTC_miscMiscellaneous events detected by the TC. The counter will count twice for each occurrenceFLUSHNumber of flushesglobal_power_eventsCounts the time during which a processor is not stoppedRUNNINGThe processor is active (includes the handling of HLT STPCLK and throttlingtc_ms_xferNumber of times that uop delivery changed from TC to MS ROMCISCA TC to MS transfer occurreduop_queue_writesNumber of valid uops written to the uop queueFROM_TC_BUILDThe uops being written are from TC build modeFROM_TC_DELIVERThe uops being written are from TC deliver modeFROM_ROMThe uops being written are from microcode ROMretired_mispred_branch_typeNumber of retiring mispredicted branches by typeCONDITIONALConditional jumpsCALLIndirect call branchesRETURNReturn branchesINDIRECTReturns, indirect calls, or indirect jumpsretired_branch_typeNumber of retiring branches by typeresource_stallOccurrences of latency or stalls in the AllocatorSBFULLA stall due to lack of store buffersWC_BufferNumber of Write Combining Buffer operationsWCB_EVICTSWC Buffer evictions of all causesWCB_FULL_EVICTWC Buffer eviction; no WC buffer is availableb2b_cyclesNumber of back-to-back bus cyclesBIT1bit 1BIT2bit 2BIT3bit 3BIT4bit 4BIT5bit 5BIT6bit 6bnrNumber of bus-not-ready conditionsBIT0bit 0snoopNumber of snoop hit modified bus trafficBIT7bit 7responseCount of different types of responsesBIT8bit 8BIT9bit 9front_end_eventNumber of retirements of tagged uops which are specified through the front-end tagging mechanismNBOGUSThe marked uops are not bogusBOGUSThe marked uops are bogusexecution_eventNumber of retirements of tagged uops which are specified through the execution tagging mechanism. The event-mask allows from one to four types of uops to be taggedNBOGUS0NBOGUS1NBOGUS2NBOGUS3BOGUS0BOGUS1BOGUS2BOGUS3replay_eventNumber of retirements of tagged uops which are specified through the replay tagging mechanismL1_LD_MISSVirtual mask for L1 cache load miss replaysL2_LD_MISSVirtual mask for L2 cache load miss replaysDTLB_LD_MISSVirtual mask for DTLB load miss replaysDTLB_ST_MISSVirtual mask for DTLB store miss replaysDTLB_ALL_MISSVirtual mask for all DTLB miss replaysBR_MSPVirtual mask for tagged mispredicted branch replaysMOB_LD_REPLAYVirtual mask for MOB load replaysSP_LD_RETVirtual mask for split load replays. Use with load_port_replay eventSP_ST_RETVirtual mask for split store replays. Use with store_port_replay eventinstr_retiredNumber of instructions retired during a clock cycleNBOGUSNTAGNon-bogus instructions that are not taggedNBOGUSTAGNon-bogus instructions that are taggedBOGUSNTAGBogus instructions that are not taggedBOGUSTAGBogus instructions that are taggeduops_retiredNumber of uops retired during a clock cycleuops_typeThis event is used in conjunction with with the front-end mechanism to tag load and store uopsTAGLOADSThe uop is a load operationTAGSTORESThe uop is a store operationbranch_retiredNumber of retirements of a branchMMNPBranch not-taken predictedMMNMBranch not-taken mispredictedMMTPBranch taken predictedMMTMBranch taken mispredictedmispred_branch_retiredNumber of retirements of mispredicted IA-32 branch instructionsThe retired instruction is not bogusx87_assistNumber of retirements of x87 instructions that required special handlingFPSUHandle FP stack underflowFPSOHandle FP stack overflowPOAOHandle x87 output overflowPOAUHandle x87 output underflowPREAHandle x87 input assistmachine_clearNumber of occurances when the entire pipeline of the machine is clearedCLEARCounts for a portion of the many cycles while the machine is cleared for any cause. Use edge-triggering for this bit only to get a count of occurances versus a durationMOCLEARIncrements each time the machine is cleared due to memory ordering issuesSMCLEARIncrements each time the machine is cleared due to self-modifying code issuesinstr_completedInstructions that have completed and retired during a clock cycle (models 3, 4, 6 only)Non-bogus instructionsBogus instructions & $ $ $           4 # #  #  # # # # #   ! !(& !" #+ $+ %+ &*'*())+**++,+-*umonitor at priv level 1, 2, 3kmonitor at priv level 0cmplcomplementeedgethrevent threshold in range [0-15][0x%lx 0x%lx 0x%lx usr=%d os=%d tag_ena=%d tag_val=%d evmask=0x%x evsel=0x%x escr_sel=0x%x comp=%d cmpl=%d thr=%d e=%d] %s %s:%s:%s=%lu??pmu: %s event%d: :: no name (prev event was %s) pmu: %s event%d: %s :: no description pmu: %s event%d:%s umask%d: %s :: no description pmu: %s event%d:%s umask%d: %s :: invalid bit field pmu: %s event%d:%s :: more than one default umask pmu: %s event%d:%s :: no event mask end-marker Pentium4netburstPentium4 (Prescott)netburst_pint^^WB8B1 W W     ( 0 8 @  H !P "X $` &h (Wp ,Wt .ex 24 3I 4 8 Ap J K L M N PW R     W^WWC      !"#$%&'()*+,-./0123456789:;<=>?θ["f12;3;@&{ ' ( ) * + pmu,( -[,idx.W0 /W4 0W8<5@A;B;C;EFGHWIW@7y 8 9 : ; < =(idx>W, ?048K5 6 7 89@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ]* ^0 (_@ (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pes[ @ ub H wm P xm X y~ ` zm h { p | x } ~    P v  m   * ?y@ P a a !h "~ s W W W W { ; W W WW W WW*  J 0 WD D P 0 p ` "p D ` m W   " D    =\ # >B?# ?B># @B=# AB<# BB;# CB7# DB'# EB!# FB  ;{ $val < G  H\  ra# sB 4# tB3# uB0# vB.# wB-# xB,# yB(# zB'# {B&# |B%# }B$# ~B"# B!# B  p$val q  a   bit ; ; %       !"#$%&'()*+,- N   ; ;  { N(^   W W W W  i&/W'/W\(i1Wl);2*e;D +={ +>,XW*eXD P'XH(iZWd(nZW`-d;.oW'o~*eoD ~(aq* @+r{ +s+t;~+u;\+vWX(nw(kxWT(idxW(bitxW(retxW+yWP+yWL/+0W1X2retWl3Wh0WD1X2retWl3Wh4,W1,X2p.h 43W13X5idx3WT2p5h4>W%1>X1>WT2p@h0EW1EH1EWD1EW@1E* 2peG`3HW\2idxHWl^0eW)1eX5idxeWT1e H2pegh2pmuh`0{W1{5fp{ 2pmu}P2pe~H3@2iWl2jWh3Wd3W`3W\0;.1X1WT3;l^>-+ /S .6 6 7 8" % $ > $ > : ; II!I/   I  : ; : ;I8 : ;  : ;  : ; I8 &I'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8  : ; !&"'# : ; I 8 $ : ; I% : ; &.: ; 'I@B': ; I(4: ; I).: ; '@B*: ; I+4: ; I,.: ; 'I@B- : ; ..?: ; 'I@B/ U0.: ;'I@B1: ;I24: ;I34: ;I4.: ;'I@B5: ;I64: ;I?74: ; I?<84: ; I?,&Tl /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_intel_netburst.ctypes.hstddef.hstdint.hstdio.hlibio.hpfmlib.hpfmlib_priv.hpfmlib_intel_netburst_priv.hpfmlib_intel_x86_priv.hintel_netburst_events.h /ux/I2=2xqtJrt Js <t Jut Jv JwRxCyBzONFP$7J$EYxuuw؃6:<fufuYv#KZKZu0u0uuv0I&0-@@8 hS`20L)K>KESi Z}9 Z ) 1 3 @ ,.H%   f xt3@pfmlib_intel_netburst.cnetburst_eventsnetburst_get_numasksnetburst_display_regnetburst_add_defaultspfm_netburst_detectpfm_netburst_detect_prescottpfm_netburst_get_event_firstpfm_netburst_get_event_nextpfm_netburst_event_is_validpfm_netburst_get_event_attr_infopfm_netburst_get_event_infopfm_netburst_validate_tablepfm_netburst_get_event_nattrsnetburst_mods__pfm_vbprintfpfm_netburst_get_encodingpfmlib_strconcatpfmlib_sort_attrpfm_intel_x86_detectpfm_intel_x86_cfgfprintfnetburst_supportpfm_netburst_get_perf_encodingpfm_netburst_perf_validate_pattrsnetburst_p_support9 2T ^p z 22 2 2 2 ( p2 p2@ `2Y hw " 2< Ky  D  * ,C R c \|   ! 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K`2Y 4 f$o |' D  y @Kl 9   4 T t@ ./751 1386324441 1009 1009 100664 26440 ` ELF>P5@@UHH H}HEHE}tEE}7u7 L2_INVALIDInvalid line from L2L2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2ALLShared, Exclusive, Owned, Modified State Refills INVALIDInvalidSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModifiedInvalid, Shared, Exclusive, Owned, Modified DATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2DATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from SystemDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITL1 DTLB Miss and L2 DTLB HitL1_DTLB_AND_L2_DTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesCPU_CLK_UNHALTEDCPU Clocks not HaltedINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissRETIRED_INSTRUCTIONSRetired Instructions (includes exceptions, interrupts, resyncs)RETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch Resyncs (only non-control transfer branches)INTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts Taken@ABCDEFGvAMD64 K7amd64_k7int^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS 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gZftYsize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEAMD64_FAM10H_REV_BAMD64_FAM10H_REV_CAMD64_FAM10H_REV_D_IO_save_endPFM_PMU_AMD64amd64_k7_data_cache_refillsPFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivpfmlib_amd64_k7.cPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXpfm_event_info_tpfm_amd64_k7_detectPFM_PMU_PPC970PFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tPFM_PMU_MIPS_R12000charmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BAMD64_K8_REV_DAMD64_K8_REV_EAMD64_K8_REV_FAMD64_K8_REV_GPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersamd64_k7_pePFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tdfl_val64PFM_DTYPE_RATIOamd64_umask_tnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1PFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encoding_flags2_IO_read_baseget_event_nextthis_unused2pfm_amd64_cfgPFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescpfm_amd64_config_tPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSAMD64_K8_REV_BPFM_PMU_SPARC_NIAGARA1_IO_write_endPFM_PMU_INTEL_PPROumasksnpattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3amd64_entry_t__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstrAMD64_CPU_UNpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEamd64_k7_supportPFM_PMU_INTEL_ATOMsteppingcan_auto_encodeget_event_attr_infosizerevisionlong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DPamd64_k7_data_cache_refills_from_system__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsamd64_modsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endmodmskAMD64_FAM14H_REV_BPFM_PMU_INTEL_X86_ARCHAMD64_K8_REV_CPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tableAMD64_K7pmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx CAC ~ .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @C?0+ &@1;2 6AHCHHT g0bf0 { kvg 0!0$4-Q4X480g4; >/@WcC   w2Pgpfmlib_amd64_k7.camd64_k7_data_cache_refillsamd64_k7_data_cache_refills_from_systemamd64_k7_pepfm_amd64_k7_detectpfm_amd64_detectpfm_amd64_cfgamd64_k7_supportamd64_modspfm_amd64_get_event_firstpfm_amd64_get_event_nextpfm_amd64_get_event_infopfm_amd64_get_event_nattrspfm_amd64_event_is_validpfm_amd64_get_event_attr_infopfm_amd64_get_encodingpfm_amd64_get_perf_encodingpfm_amd64_perf_validate_pattrspfm_amd64_validate_table( ) @HPhpx  (*@DHQ`nhw@H`h(: L _ 0 8 @ @` h p @   + D ] q ( P X     / L j  @ H p x  8 h    0 G8 e` h     @ p  h  !C) 0 7 >  E YL S a f  q ~  I     3  : >     9 ) ~ 6  C <P 3] tj w   x ;   G C  g          - W : H O [ g  s b .     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' I ' d   y {' E i' m ,'  '  i'  '   + {V' A (F (G (H (I (J (K ) O *) % $ > $ > : ; I  I : ; : ;I8 : ;  : ;  : ; I8 I !I/ &I'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8  : ; !&"'#.: ; 'I@B$: ; I%4: ; I&4: ; I'4: ;I(4: ; I?)4: ; I?<*!,< /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_amd64_k8.ctypes.hstddef.hstdint.hstdio.hlibio.hpfmlib.hpfmlib_priv.hpfmlib_amd64_priv.hamd64_events_k8.h JXtX/JXtX/JXtX/JXtX/JXtX/JXtXsize_tsizetypeamd64_k8_gartpfm_amd64_cfgvalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEamd64_k8_dcache_misses_by_locked_instructionsAMD64_FAM10H_REV_BAMD64_FAM10H_REV_CAMD64_FAM10H_REV_Damd64_k8_revc_support_IO_save_endPFM_PMU_AMD64amd64_k8_fpu_exceptionsPFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2amd64_k8_prefetch_instructions_dispatchedPFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainamd64_k8_sized_blocksPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEamd64_k8_memory_requestsnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34K_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1amd64_k8_data_cache_refillsngrpPFM_DTYPE_MAXpfm_event_info_tPFM_PMU_PPC970PFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEos_datapmu_terminateunsigned charamd64_k8_memory_controller_bypassPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXamd64_k8_dram_accesses_pagectrlpfm_amd64_k8_reve_detectPFM_PMU_MIPS_R10000amd64_k8_revd_supportPFM_PMU_INTEL_SNBEP_UNC_R2PCIEpfm_pmu_tamd64_k8_dispatched_fpuPFM_PMU_MIPS_R12000charmodeldfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tpfmlib_amd64_k8.camd64_k8_thermal_status_and_ecc_errorsPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BAMD64_K8_REV_DAMD64_K8_REV_EAMD64_K8_REV_FAMD64_K8_REV_GPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KC_posPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3pfm_amd64_k8_revb_detect_markersPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tdfl_val64PFM_DTYPE_RATIOamd64_umask_tnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1PFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176amd64_k8_sized_commandsPFM_PMU_CELLpfm_pmu_type_tPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encodingamd64_k8_hypertransport_link0_flags2_IO_read_baseget_event_nextthis_unused2amd64_k8_probePFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescpfm_amd64_config_tPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPamd64_k8_reve_supportPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSAMD64_K8_REV_BPFM_PMU_SPARC_NIAGARA1pfm_amd64_k8_revg_detect_IO_write_endPFM_PMU_INTEL_PPROumasksamd64_k8_memory_controller_turnaroundsamd64_k8_requests_to_l2npattrscountdfl_boolevent_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3amd64_entry_t__pad1__pad2__pad3__pad4__pad5_sbufis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsPFM_PMU_S390X_CPUM_CFpfm_amd64_k8_revd_detect_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstrAMD64_CPU_UNpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMamd64_k8_data_prefetchesamd64_k8_segment_register_loadssteppingcan_auto_encodeget_event_attr_infoamd64_k8_data_cache_refills_from_systemsizerevisionlong long unsigned intamd64_k8_cpu_io_requests_to_memory_ioPFM_DTYPE_CHAR8pattrsamd64_k8_revf_supportPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12amd64_k8_l2_fill_writebackPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descamd64_k8_retired_fastpath_double_op_instructionsPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREamd64_k8_retired_mmx_and_fp_instructions_next__off64_tcodedtypeget_event_nattrsamd64_modsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Iosidamd64_k8_revb_supportPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesamd64_k8_scrubber_single_bit_ecc_errorsamd64_k8_l2_cache_missget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsamd64_k8_peamd64_k8_quadwords_written_to_systemPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAXpfm_amd64_k8_revf_detect_IO_read_endmodmskAMD64_FAM14H_REV_BPFM_PMU_INTEL_X86_ARCHAMD64_K8_REV_CPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoamd64_k8_cache_blockamd64_k8_revg_supportreservedamd64_k8_system_read_responsesPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tableAMD64_K7pmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24Kamd64_k8_locked_opsPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_amd64_k8_revc_detectpfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx CAC ~ <CAC ~ \CAC ~ |CAC ~ CAC ~ CAC ~ .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @ + &ؙ 1;M 6.HUC(&Tigk0b0 {kv0 0m0-Մ؄H02 + K _`x @ `  @<` `U t @ ` =Uq`  2"J`% Y 'g@(<PCCCCC COC   '8F\g8Wppfmlib_amd64_k8.camd64_k8_dispatched_fpuamd64_k8_segment_register_loadsamd64_k8_locked_opsamd64_k8_memory_requestsamd64_k8_data_cache_refillsamd64_k8_data_cache_refills_from_systemamd64_k8_scrubber_single_bit_ecc_errorsamd64_k8_prefetch_instructions_dispatchedamd64_k8_dcache_misses_by_locked_instructionsamd64_k8_data_prefetchesamd64_k8_system_read_responsesamd64_k8_quadwords_written_to_systemamd64_k8_requests_to_l2amd64_k8_l2_cache_missamd64_k8_l2_fill_writebackamd64_k8_retired_mmx_and_fp_instructionsamd64_k8_retired_fastpath_double_op_instructionsamd64_k8_fpu_exceptionsamd64_k8_dram_accesses_pageamd64_k8_memory_controller_turnaroundsamd64_k8_memory_controller_bypassamd64_k8_sized_blocksamd64_k8_thermal_status_and_ecc_errorsamd64_k8_cpu_io_requests_to_memory_ioamd64_k8_cache_blockamd64_k8_sized_commandsamd64_k8_probeamd64_k8_gartamd64_k8_hypertransport_link0amd64_k8_pepfm_amd64_k8_revb_detectpfm_amd64_k8_revc_detectpfm_amd64_k8_revd_detectpfm_amd64_k8_reve_detectpfm_amd64_k8_revf_detectpfm_amd64_k8_revg_detectpfm_amd64_detectpfm_amd64_cfgamd64_k8_revb_supportamd64_modspfm_amd64_get_event_firstpfm_amd64_get_event_nextpfm_amd64_get_event_infopfm_amd64_get_event_nattrspfm_amd64_event_is_validpfm_amd64_get_event_attr_infopfm_amd64_get_encodingpfm_amd64_get_perf_encodingpfm_amd64_perf_validate_pattrspfm_amd64_validate_tablepfm_amd64_get_num_eventsamd64_k8_revc_supportamd64_k8_revd_supportamd64_k8_reve_supportamd64_k8_revf_supportamd64_k8_revg_support2(3W2k32323 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SINGLE_ADD_SUB_OPSSingle precision add/subtract opsSINGLE_MUL_OPSSingle precision multiply opsSINGLE_DIV_OPSSingle precision divide/square root opsDOUBLE_ADD_SUB_OPSDouble precision add/subtract opsDOUBLE_MUL_OPSDouble precision multiply opsDOUBLE_DIV_OPSDouble precision divide/square root opsOP_TYPEOp type: 0=uops. 1=FLOPS @ LOW_QW_MOVE_UOPSMerging low quadword move uopsHIGH_QW_MOVE_UOPSMerging high quadword move uopsALL_OTHER_MERGING_MOVE_UOPSAll other merging move uopsALL_OTHER_MOVE_UOPSAll other move uops SSE_BOTTOM_EXECUTING_UOPSSSE bottom-executing uops retiredSSE_BOTTOM_SERIALIZING_UOPSSSE bottom-serializing uops retiredX87_BOTTOM_EXECUTING_UOPSX87 bottom-executing uops retiredX87_BOTTOM_SERIALIZING_UOPSX87 bottom-serializing uops retired BOTTOM_EXECUTE_CYCLESNumber of cycles a bottom-execute uop is in the FP schedulerBOTTOM_SERIALIZING_CYCLESNumber of cycles a bottom-serializing uop is in the FP scheduler ESCSSSDSFSGSHS @ EXECUTEDThe number of locked instructions executedCYCLES_SPECULATIVE_PHASEThe number of cycles spent in speculative phaseCYCLES_NON_SPECULATIVE_PHASEThe number of cycles spent in non-speculative phase (including cache miss penalty)CYCLES_WAITINGThe number of cycles waiting for a cache hit (cache miss penalty). ADDRESS_MISMATCHESAddress mismatches (starting byte not the same).STORE_IS_SMALLER_THAN_LOADStore is smaller than load.MISALIGNEDMisaligned. SYSTEMRefill from the NorthbridgeL2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2 INVALIDInvalidSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModified BY_PREFETCHNTACache line evicted was brought into the cache with by a PrefetchNTA instruction.NOT_BY_PREFETCHNTACache line evicted was not brought into the cache with by a PrefetchNTA instruction. @ L2_4K_TLB_HITL2 4K TLB hitL2_2M_TLB_HITL2 2M TLB hitL2_1G_TLB_HITL2 1G TLB hit   4K_TLB_RELOAD4K TLB reload2M_TLB_RELOAD2M TLB reload1G_TLB_RELOAD1G TLB reload SCRUBBER_ERRORScrubber errorPIGGYBACK_ERRORPiggyback scrubber errorsLOAD_PIPE_ERRORLoad pipe errorSTORE_WRITE_PIPE_ERRORStore write pipe error LOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA) DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONSData cache misses by locked instructions L1_4K_TLB_HITL1 4K TLB hitL1_2M_TLB_HITL1 2M TLB hitL1_1G_TLB_HITL1 1G TLB hit SW_PREFETCH_HIT_IN_L1Software prefetch hit in the L1.SW_PREFETCH_HIT_IN_L2Software prefetch hit in L2. NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memorySTREAMING_STOREStreaming store (SS) requests CANCELLEDCancelled prefetchesATTEMPTEDPrefetch attempts BUFFER_0Buffer 0BUFFER_1Buffer 1BUFFER_2Buffer 2BUFFER_3Buffer 3BUFFER_4Buffer 4BUFFER_5Buffer 5BUFFER_6Buffer 6BUFFER_7Buffer 7BUFFER_8Buffer 8BUFFER_9Buffer 9 DATA_ERRORData Error QUADWORD_WRITE_TRANSFEROctword write transfer INSTRUCTIONSIC fillDATADC fillTLB_WALKTLB fill (page table walks)SNOOPTag snoop requestCancelled requestHW_PREFETCH_FROM_DCHardware prefetch from DC ? DC fill (includes possible replays, whereas EventSelect 041h does not)TLB page table walk L2_FILLSL2 fills (victims from L1 caches, TLB page table walks and data prefetches)L2_WRITEBACKSL2 Writebacks to system. 4K_PAGE_FETCHESInstruction fetches to a 4K page.2M_PAGE_FETCHESInstruction fetches to a 2M page. INVALIDATING_PROBE_NO_IN_FLIGHTInvalidating probe that did not hit any in-flight instructions.INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHTInvalidating probe that hit one or more in-flight instructions. X87X87 instructionsMMX_AND_3DNOWMMX and 3DNow! instructionsPACKED_SSE_AND_SSE2SSE instructions (SSE, SSE2, SSE3, and SSE4A) POSITION_0With low op in position 0POSITION_1With low op in position 1POSITION_2With low op in position 2 X87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtraps HITDCT0 Page hitMISSDCT0 Page MissCONFLICTDCT0 Page ConflictDCT1_PAGE_HITDCT1 Page hitDCT1_PAGE_MISSDCT1 Page MissDCT1_PAGE_CONFLICTDCT1 Page Conflict ? DCT0_PAGE_TABLE_OVERFLOWDCT0 Page Table OverflowDCT1_PAGE_TABLE_OVERFLOWDCT1 Page Table Overflow DCT0_COMMAND_SLOTS_MISSEDDCT0 Command Slots MissedDCT1_COMMAND_SLOTS_MISSEDDCT1 Command Slots Missed CHIP_SELECTDCT0 DIMM (chip select) turnaroundREAD_TO_WRITEDCT0 Read to write turnaroundWRITE_TO_READDCT0 Write to read turnaroundDCT1_DIMMDCT1 DIMM (chip select) turnaroundDCT1_READ_TO_WRITE_TURNAROUNDDCT1 Read to write turnaroundDCT1_WRITE_TO_READ_TURNAROUNDDCT1 Write to read turnaround ? HIGH_PRIORITYMemory controller high priority bypassLOW_PRIORITYMemory controller medium priority bypassDRAM_INTERFACEDCT0 DCQ bypassDRAM_QUEUEDCT1 DCQ bypass CLKS_DIE_TEMP_TOO_HIGHNumber of times the HTC trip point is crossedCLKS_TEMP_THRESHOLD_EXCEEDEDNumber of clocks when STC trip point activeSTC_TRIP_POINTS_CROSSEDNumber of times the STC trip point is crossedCLOCKS_HTC_P_STATE_INACTIVENumber of clocks HTC P-state is inactive.CLOCKS_HTC_P_STATE_ACTIVENumber of clocks HTC P-state is active @| I_O_TO_I_OIO to IOI_O_TO_MEMIO to MemCPU_TO_I_OCPU to IOCPU_TO_MEMCPU to MemTO_REMOTE_NODETo remote nodeTO_LOCAL_NODETo local nodeFROM_REMOTE_NODEFrom remote nodeFROM_LOCAL_NODEFrom local node @ VICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSRead Block (Dcache load miss refill)SHARED_ICACHE_REFILLRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)READ_TO_DIRTYChange-to-Dirty (first store to clean block already in cache) = NON_POSTED_WRITE_BYTENon-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytesNON_POSTED_WRITE_DWORDNon-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORDPOSTED_WRITE_BYTEPosted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPOSTED_WRITE_DWORDPosted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesREAD_BYTE_4_BYTESSzRd Byte (4 bytes) Legacy or mapped IOREAD_DWORD_1_16_DWORDSSzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size ? Probe missHIT_CLEANProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_DISPLAY_REFRESH_READSUpstream display refresh/ISOC readsUPSTREAM_NON_DISPLAY_REFRESH_READSUpstream non-display refresh readsUPSTREAM_WRITESUpstream ISOC writesUPSTREAM_NON_ISOC_WRITESUpstream non-ISOC writes @ APERTURE_HIT_FROM_CPUGART aperture hit on access from CPUAPERTURE_HIT_FROM_IOGART aperture hit on access from IOGART missREQUEST_HIT_TABLE_WALKGART/DEV Request hit table walk in progressDEV_HITDEV hitDEV_MISSDEV missDEV_ERRORDEV errorMULTIPLE_TABLE_WALKGART/DEV multiple table walk in progress @ WRITE_REQUESTSWrite requests sent to the DCTREAD_REQUESTSRead requests (including prefetch requests) sent to the DCTPREFETCH_REQUESTSPrefetch requests sent to the DCT32_BYTES_WRITES32 Bytes Sized Writes64_BYTES_WRITES64 Bytes Sized Writes32_BYTES_READS32 Bytes Sized Reads64_BYTES_READS64 Byte Sized ReadsREAD_REQUESTS_WHILE_WRITES_REQUESTSRead requests sent to the DCT while writes requests are pending in the DCT @ LOCAL_TO_0From Local node to Node 0LOCAL_TO_1From Local node to Node 1LOCAL_TO_2From Local node to Node 2LOCAL_TO_3From Local node to Node 3LOCAL_TO_4From Local node to Node 4LOCAL_TO_5From Local node to Node 5LOCAL_TO_6From Local node to Node 6LOCAL_TO_7From Local node to Node 7 @ READ_BLOCKRead blockREAD_BLOCK_SHAREDRead block sharedRead block modifiedCHANGE_TO_DIRTYChange-to-Dirty @  @ READ_SIZEDRead SizedWRITE_SIZEDWrite SizedVICTIM_BLOCKVictim BlockNODE_GROUP_SELECTNode Group Select. 0=Nodes 0-3. 1= Nodes 4-7.LOCAL_TO_0_4From Local node to Node 0/4LOCAL_TO_1_5From Local node to Node 1/5LOCAL_TO_2_6From Local node to Node 2/6LOCAL_TO_3_7From Local node to Node 3/7 @ COMMAND_DWORD_SENTCommand DWORD sentDATA_DWORD_SENTData DWORD sentBUFFER_RELEASE_DWORD_SENTBuffer release DWORD sentNOP_DWORD_SENTNop DW sent (idle)ADDRESS_EXT_DWORD_SENTAddress extension DWORD sentPER_PACKET_CRC_SENTPer packet CRC sentSUBLINK_MASKSubLink Mask ? Address DWORD sent ? READ_BLOCK_EXCLUSIVERead Block Exclusive (Data cache read)Read Block Shared (Instruction cache read)READ_BLOCK_MODIFYRead Block ModifyANY_READAny read modes (exclusive, shared, modify)ALL_CORES All cores ANY_STATEAny line state (shared, owned, exclusive, modified)  GUEST_LARGERGuest page size is larger than the host page size.MTRR_MISMATCHMTRR mismatch.HOST_LARGERHost page size is larger than the guest page size. ADD_SUB_OPSAdd/subtract opsMUL_OPSMultiply opsDIV_OPSDivide ops DISPATCHED_FPUDispatched FPU OperationsCYCLES_NO_FPU_OPS_RETIREDCycles in which the FPU is EmptyDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsRETIRED_SSE_OPERATIONSRetired SSE OperationsRETIRED_MOVE_OPSRetired Move OpsRETIRED_SERIALIZING_OPSRetired Serializing OpsFP_SCHEDULER_CYCLESNumber of Cycles that a Serializing uop is in the FP SchedulerSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitLS_BUFFER_2_FULL_CYCLESLS Buffer 2 FullLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsCANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONSCancelled Store to Load Forward OperationsSMIS_RECEIVEDSMIs ReceivedDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or NorthbridgeDATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from the NorthbridgeDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITL1 DTLB Miss and L2 DTLB HitL1_DTLB_AND_L2_DTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesMICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESSMicroarchitectural Late Cancel of an AccessMICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESSMicroarchitectural Early Cancel of an AccessSCRUBBER_SINGLE_BIT_ECC_ERRORSSingle-bit ECC Errors Recorded by ScrubberPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsL1_DTLB_HITL1 DTLB HitINEFFECTIVE_SW_PREFETCHESIneffective Software PrefetchesGLOBAL_TLB_FLUSHESGlobal TLB FlushesMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHESData PrefetcherMAB_REQUESTSAverage L1 refill latency for Icache and Dcache misses (request count for cache refills)MAB_WAIT_CYCLESAverage L1 refill latency for Icache and Dcache misses (cycles that requests spent waiting for the refills)SYSTEM_READ_RESPONSESNorthbridge Read Responses by Coherency StateQUADWORDS_WRITTEN_TO_SYSTEMOctwords Written to SystemCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsINSTRUCTION_CACHE_LINES_INVALIDATEDInstruction Cache Lines InvalidatedITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB Reloads AbortedRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_AND_FP_INSTRUCTIONSRetired MMX/FP InstructionsRETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSRetired Fastpath Double Op InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_BRANCH_ABORTDispatch Stall for Branch Abort to RetireDISPATCH_STALL_FOR_SERIALIZATIONDispatch Stall for SerializationDISPATCH_STALL_FOR_SEGMENT_LOADDispatch Stall for Segment LoadDISPATCH_STALL_FOR_REORDER_BUFFER_FULLDispatch Stall for Reorder Buffer FullDISPATCH_STALL_FOR_RESERVATION_STATION_FULLDispatch Stall for Reservation Station FullDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FPU FullDISPATCH_STALL_FOR_LS_FULLDispatch Stall for LS FullDISPATCH_STALL_WAITING_FOR_ALL_QUIETDispatch Stall Waiting for All QuietDISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNCDispatch Stall for Far Transfer or Resync to RetireFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesDRAM_ACCESSES_PAGEDRAM AccessesMEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWSDRAM Controller Page Table OverflowsMEMORY_CONTROLLER_SLOT_MISSESMemory Controller DRAM Command Slots MissedMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_BYPASSMemory Controller Bypass Counter SaturationTHERMAL_STATUS_AND_ECC_ERRORSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsPROBEProbe Responses and Upstream RequestsGARTGART EventsMEMORY_CONTROLLER_REQUESTSMemory Controller RequestsCPU_TO_DRAM_REQUESTS_TO_TARGET_NODECPU to DRAM Requests to Target NodeIO_TO_DRAM_REQUESTS_TO_TARGET_NODEIO to DRAM Requests to Target NodeCPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3CPU Read Command Latency to Target Node 0-3CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3CPU Read Command Requests to Target Node 0-3CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7CPU Read Command Latency to Target Node 4-7CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7CPU Read Command Requests to Target Node 4-7CPU_COMMAND_LATENCY_TO_TARGET_NODE_0_3_4_7CPU Command Latency to Target Node 0-3/4-7CPU_REQUESTS_TO_TARGET_NODE_0_3_4_7CPU Requests to Target Node 0-3/4-7HYPERTRANSPORT_LINK0HyperTransport Link 0 Transmit BandwidthHYPERTRANSPORT_LINK1HyperTransport Link 1 Transmit BandwidthHYPERTRANSPORT_LINK2HyperTransport Link 2 Transmit BandwidthHYPERTRANSPORT_LINK3HyperTransport Link 3 Transmit BandwidthREAD_REQUEST_TO_L3_CACHERead Request to L3 CacheL3_CACHE_MISSESL3 Cache MissesL3_FILLS_CAUSED_BY_L2_EVICTIONSL3 Fills caused by L2 EvictionsL3_EVICTIONSL3 EvictionsPAGE_SIZE_MISMATCHESPage Size MismatchesRETIRED_X87_OPSRetired x87 Floating Point OperationsIBS_OPS_TAGGEDIBS Ops TaggedLFENCE_INST_RETIREDLFENCE Instructions RetiredSFENCE_INST_RETIREDSFENCE Instructions RetiredMFENCE_INST_RETIREDMFENCE Instructions RetiredNON_CANCELLED_L3_READ_REQUESTSNon-cancelled L3 Read Requests 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' *  ? {}' (U /(F (G (H ) O *) Ѻ% $ > $ > : ; I  I : ; : ;I8 : ;  : ;  : ; I8 I !I/ &I'II : ; ( : ;I : ; : ;I 8  : ;I8  I8  : ; : ;I : ;  : ;  : ; I : ; I8  : ;  : ; I8  : ; !&"'#.: ; 'I@B$: ; I%4: ; I&4: ; I'4: ;I(4: ; I?)4: ; I?<*!,D /usr/include/bits/usr/lib/gcc/x86_64-redhat-linux/4.7.2/include/usr/include/home/reissman/papi-5.3.0/src/libpfm4/lib/../include/perfmoneventspfmlib_amd64_fam10h.ctypes.hstddef.hstdint.hstdio.hlibio.hpfmlib.hpfmlib_priv.hpfmlib_amd64_priv.hamd64_events_fam10h.h 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unsigned intmax_encoding_flags2_IO_read_baseget_event_nextthis_unused2pfm_amd64_cfgamd64_fam10h_locked_opsPFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescpfm_amd64_config_tPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPamd64_fam10h_peamd64_fam10h_l1_dtlb_miss_and_l2_dtlb_hitPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSAMD64_K8_REV_BPFM_PMU_SPARC_NIAGARA1amd64_fam10h_fp_scheduler_cycles_IO_write_endamd64_fam10h_ineffective_sw_prefetchesamd64_fam10h_thermal_status_and_ecc_errorsPFM_PMU_INTEL_PPROumasksnpattrscountdfl_booleventamd64_fam10h_cache_block_IO_buf_baseamd64_fam10h_hypertransport_link0amd64_fam10h_hypertransport_link3unsigned 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intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12amd64_fam10h_dcache_misses_by_locked_instructionsPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tamd64_fam10h_memory_controller_page_table_overflowscodepfmlib_amd64_fam10h.camd64_fam10h_memory_controller_turnaroundsdtypeget_event_nattrsamd64_modsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesamd64_fam10h_istanbul_supportget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HAamd64_fam10h_retired_move_opspfm_attr_treserved_bitsamd64_fam10h_requests_to_l2amd64_fam10h_l2_fill_writebackPFM_PMU_INTEL_SNBEP_UNC_PCUamd64_fam10h_shanghai_supportPFM_OS_MAX_IO_read_endmodmskAMD64_FAM14H_REV_BPFM_PMU_INTEL_X86_ARCHAMD64_K8_REV_CPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoreservedPFM_PMU_INTEL_NHM_EXshort unsigned intamd64_fam10h_retired_mmx_and_fp_instructionsdfl_intvalidate_tableAMD64_K7pmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPamd64_fam10h_read_request_to_l3_cachePFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmamd64_fam10h_data_cache_refillspfmlib_event_desc_tamd64_fam10h_gartamd64_fam10h_cpu_read_command_latency_to_target_node_4_7GCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx CAC ~ <CAC ~ \CAC ~ .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @+  &(1 ;  68PXHC6X)TƟg0b_0 {v` 00ž-x(`HppI `7 3Wu `   /`O{ K@}  `@` @4@]`y `!`#`$<%q@&')`)` +7 -]@/0 @369 <  > 4@A eB D `F H1ISKy`L`M NO`Pm,CNCCoC    % @ Y w       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D0 E~7 EO> E6E E L ES Ea EBf E}q E>~ E EV E E( E E E E_ E E E E  E E E5) E6 E0C EP E] Ej E w E E) E  E  E Eu E E" E  E E E E  E- E: E+ H EO Er[ E8g Es E0  E_ Em  E  E E  E! E=  E E  E E~  E% E" E( E. E04 E:: E@ EF EL E+R E,X Ea^ E d ERj Ep EBv EZ | E  Ex E  E  E[ En E E^  E EC E E E) E  E E EM  E  E  E  E E  E  E_  E Eh E E$ E* E0 E6 E< EB E H EN Ez T E [ Eb Ei E5 p Ew E~ E  E Es E  Er E Ef E E E E E E E E E  E' EC E EE  Eb  E  E  Ey& E"- E?4 EV; EB E I E P EW E^ E1 e E l Es Ez E E< EV E"  EK E E E Ew E E Ek  EQ E  EV E Ep E  E% E! E' E- E 3 E9 Ek ? E?E EaL E _ Ee Ek Ehq Ex E E En  E< E Eo E% E0 E E EY  E E|1 EK EX E1l Eo E E% E0 Ea  E! E E E E EY E) E|6 EP Ej E ~ E E E E  E' Eh  E E E E+ E7 EC EO E [ EOh Eu E Eh E E E E EW E E E E E Ex! E8 ED EP E \ Eph E;t E E E E E E E EA E^ E E EcA E E E E E E E E{  E! E- E9 E|E E Q E ] Ei E\ Ew E E E E E E E E El E E E E E E  Ex E ! E+3CB E& _ EiCq E&  E} E&  E& E!? EKY Ee E  E  EB   E   E`& E3A E0N \ E iw E E/ E E4 E  EC ) E6@D E[Qo E|  E E  E>` E EZ  E!, E(9#G EbT$b EBo%} E/@& E' EH) E) E+ E - Ej,@/J E>W0e Er@3 EB 6 EN 9 E< E3> E@A EB" E/D= E[J`FX EeHs EI EK E `L EK`M E  N EO E"`P@ E Mm[ EXgKp E|X EY E4  E AQ @C`/812 1386324441 1009 1009 100664 60416 ` ELF>0@@UHH H}HEHE}tEE}IuIWOPS_ADDAdd pipe ops excluding load ops and SSE move opsOPS_MULTIPLYMultiply pipe ops excluding load ops and SSE move opsOPS_STOREStore pipe ops excluding load ops and SSE move opsOPS_ADD_PIPE_LOAD_OPSAdd pipe load ops and SSE move opsOPS_MULTIPLY_PIPE_LOAD_OPSMultiply pipe load ops and SSE move opsOPS_STORE_PIPE_LOAD_OPSStore pipe load ops and SSE move opsALLAll sub-events selected ? ESCSSSDSFSGSHS @ EXECUTEDThe number of locked instructions executedCYCLES_SPECULATIVE_PHASEThe number of cycles spent in speculative phaseCYCLES_NON_SPECULATIVE_PHASEThe number of cycles spent in non-speculative phase (including cache miss penalty) SYSTEMRefill from the NorthbridgeL2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2 INVALIDInvalidSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModified  SCRUBBER_ERRORScrubber errorPIGGYBACK_ERRORPiggyback scrubber errors LOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA) DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONSData cache misses by locked instructions NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memorySTREAMING_STOREStreaming store (SS) requests CANCELLEDCancelled prefetchesATTEMPTEDPrefetch attempts DATA_ERRORData Error QUADWORD_WRITE_TRANSFERQuadword write transfer INSTRUCTIONSIC fillDATADC fillTLB_WALKTLB fill (page table walks)SNOOPTag snoop requestCancelled request DC fill (includes possible replays, whereas EventSelect 041h does not)TLB page table walk L2_FILLSL2 fills (victims from L1 caches, TLB page table walks and data prefetches)L2_WRITEBACKSL2 Writebacks to system. X87X87 instructionsMMX_AND_3DNOWMMX and 3DNow! instructionsPACKED_SSE_AND_SSE2Packed SSE and SSE2 instructionsSCALAR_SSE_AND_SSE2Scalar SSE and SSE2 instructions POSITION_0With low op in position 0POSITION_1With low op in position 1POSITION_2With low op in position 2 FIXED_AND_LPAFixed and LPALPASMINMIINITSTARTUPINTEOI @ HALTSTOPGRANTSHUTDOWNWBINVDINVD X87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtraps DCT0_PAGE_HITDCT0 Page hitDCT0_PAGE_MISSDCT0 Page MissDCT0_PAGE_CONFLICTDCT0 Page ConflictDCT1_PAGE_HITDCT1 Page hitDCT1_PAGE_MISSDCT1 Page MissDCT1_PAGE_CONFLICTDCT1 Page ConflictWRITE_REQUESTWrite request.READ_REQUESTRead request. @ DCT_PAGE_TABLE_OVERFLOWDCT Page Table OverflowSTALE_TABLE_ENTRY_HITSNumber of stale table entry hits. (hit on a page closed too soon).PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTEDPage table idle cycle limit incremented.PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTEDPage table idle cycle limit decremented. DCT0_READ_TO_WRITEDCT0 read-to-write turnaround.DCT0_WRITE_TO_READDCT0 write-to-read turnaroundDCT0_DIMMDCT0 DIMM (chip select) turnaroundDCT1_READ_TO_WRITEDCT1 read-to-write turnaround.DCT1_WRITE_TO_READDCT1 write-to-read turnaroundDCT1_DIMMDCT1 DIMM (chip select) turnaround ? COUNTER_REACHEDF2x[1,0]94[DcqBypassMax] counter reached. MEMHOT_L_ASSERTIONSNumber of clocks MEMHOT_L is asserted.HTC_TRANSITIONSNumber of times the HTC transitions from inactive to active.CLOCKS_HTC_P_STATE_INACTIVENumber of clocks HTC P-state is inactive.CLOCKS_HTC_P_STATE_ACTIVENumber of clocks HTC P-state is activePROCHOT_L_ASSERTIONSPROCHOT_L asserted by an external source and the assertion causes a P-state change. @ I_O_TO_I_OIO to IOI_O_TO_MEMIO to MemCPU_TO_I_OCPU to IOCPU_TO_MEMCPU to Mem VICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSRead Block (Dcache load miss refill)SHARED_ICACHE_REFILLRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)READ_TO_DIRTYChange-to-Dirty (first store to clean block already in cache) = NON_POSTED_WRITE_BYTENon-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytesNON_POSTED_WRITE_DWORDNon-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORDPOSTED_WRITE_BYTEPosted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPOSTED_WRITE_DWORDPosted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesREAD_BYTE_4_BYTESSzRd Byte (4 bytes) Legacy or mapped IOREAD_DWORD_1_16_DWORDSSzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size ? MISSProbe missHIT_CLEANProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_DISPLAY_REFRESH_READSUpstream display refresh/ISOC reads.UPSTREAM_NON_DISPLAY_REFRESH_READSUpstream non-display refresh reads.UPSTREAM_ISOC_WRITESUpstream ISOC writes.UPSTREAM_NON_ISOC_WRITESUpstream non-ISOC writes. @ DEV_HITDEV hitDEV_MISSDEV missDEV_ERRORDEV error @p 32_BYTES_WRITES32 Bytes Sized Writes64_BYTES_WRITES64 Bytes Sized Writes32_BYTES_READS32 Bytes Sized Reads64_BYTES_READS64 Byte Sized Reads @x COMMAND_DWORD_SENTCommand DWORD sentADDRESS_DWORD_SENTAddress DWORD sentDATA_DWORD_SENTData DWORD sentBUFFER_RELEASE_DWORD_SENTBuffer release DWORD sentNOP_DWORD_SENTNop DW sent (idle)PER_PACKET_CRC_SENTPer packet CRC sent ? DISPATCHED_FPUDispatched FPU OperationsCYCLES_NO_FPU_OPS_RETIREDCycles in which the FPU is EmptyDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitLS_BUFFER_2_FULL_CYCLESLS Buffer 2 FullLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or SystemDATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from the SystemDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITNumber of data cache accesses that miss in L1 DTLB and hit in L2 DTLBL1_DTLB_AND_L2_DTLB_MISSNumber of data cache accesses that miss both the L1 and L2 DTLBsMISALIGNED_ACCESSESMisaligned AccessesMICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESSMicroarchitectural Late Cancel of an AccessMICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESSMicroarchitectural Early Cancel of an AccessSCRUBBER_SINGLE_BIT_ECC_ERRORSSingle-bit ECC Errors Recorded by ScrubberPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHESData PrefetcherSYSTEM_READ_RESPONSESSystem Read Responses by Coherency StateQUADWORDS_WRITTEN_TO_SYSTEMQuawords Written to SystemCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_AND_FP_INSTRUCTIONSRetired MMX/FP InstructionsRETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSRetired Fastpath Double Op InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_BRANCH_ABORTDispatch Stall for Branch Abort to RetireDISPATCH_STALL_FOR_SERIALIZATIONDispatch Stall for SerializationDISPATCH_STALL_FOR_SEGMENT_LOADDispatch Stall for Segment LoadDISPATCH_STALL_FOR_REORDER_BUFFER_FULLDispatch Stall for Reorder Buffer FullDISPATCH_STALL_FOR_RESERVATION_STATION_FULLDispatch Stall for Reservation Station FullDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FPU FullDISPATCH_STALL_FOR_LS_FULLDispatch Stall for LS FullDISPATCH_STALL_WAITING_FOR_ALL_QUIETDispatch Stall Waiting for All QuietDISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNCDispatch Stall for Far Transfer or Resync to RetireFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesDRAM_ACCESSESDRAM AccessesDRAM_CONTROLLER_PAGE_TABLE_EVENTSDRAM Controller Page Table EventsMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_RBD_QUEUEMemory Controller RBD Queue EventsTHERMAL_STATUSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsPROBEProbe Responses and Upstream RequestsDEVDEV EventsHYPERTRANSPORT_LINK0HyperTransport Link 0 Transmit BandwidthMEMORY_CONTROLLER_REQUESTSMemory Controller RequestsSIDEBAND_SIGNALSSideband Signals and Special CyclesInterrupt Events !"#$&'@ABCDEFGHIJKLeglmv}~   AMD64 Fam11h Turionamd64_fam11h_turionaint^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ 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.symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @Cؒ0+ &1;R 64HSeC"Tfg9h0b0 {ihzv 0i(0 -888p1 ،3Wo`  ; @m @ `  @`*`Iv   M`x@` `"%( $*5 +],APC   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SINGLE_ADD_SUB_OPSSingle precision add/subtract opsSINGLE_MUL_OPSSingle precision multiply opsSINGLE_DIV_OPSSingle precision divide/square root opsDOUBLE_ADD_SUB_OPSDouble precision add/subtract opsDOUBLE_MUL_OPSDouble precision multiply opsDOUBLE_DIV_OPSDouble precision divide/square root opsOP_TYPEOp type: 0=uops. 1=FLOPS @ LOW_QW_MOVE_UOPSMerging low quadword move uopsHIGH_QW_MOVE_UOPSMerging high quadword move uopsALL_OTHER_MERGING_MOVE_UOPSAll other merging move uopsALL_OTHER_MOVE_UOPSAll other move uops SSE_BOTTOM_EXECUTING_UOPSSSE bottom-executing uops retiredSSE_BOTTOM_SERIALIZING_UOPSSSE bottom-serializing uops retiredX87_BOTTOM_EXECUTING_UOPSX87 bottom-executing uops retiredX87_BOTTOM_SERIALIZING_UOPSX87 bottom-serializing uops retired BOTTOM_EXECUTE_CYCLESNumber of cycles a bottom-execute uop is in the FP schedulerBOTTOM_SERIALIZING_CYCLESNumber of cycles a bottom-serializing uop is in the FP scheduler ESCSSSDSFSGSHS @ EXECUTEDThe number of locked instructions executedCYCLES_SPECULATIVE_PHASEThe number of cycles spent in speculative phaseCYCLES_NON_SPECULATIVE_PHASEThe number of cycles spent in non-speculative phase (including cache miss penalty)CYCLES_WAITINGThe number of cycles waiting for a cache hit (cache miss penalty). ADDRESS_MISMATCHESAddress mismatches (starting byte not the same).STORE_IS_SMALLER_THAN_LOADStore is smaller than load.MISALIGNEDMisaligned. SYSTEMRefill from the NorthbridgeL2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2 INVALIDInvalidSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModified BY_PREFETCHNTACache line evicted was brought into the cache with by a PrefetchNTA instruction.NOT_BY_PREFETCHNTACache line evicted was not brought into the cache with by a PrefetchNTA instruction. @ L2_4K_TLB_HITL2 4K TLB hitL2_2M_TLB_HITL2 2M TLB hitL2_1G_TLB_HITL2 1G TLB hit 4K_TLB_RELOAD4K TLB reload2M_TLB_RELOAD2M TLB reload1G_TLB_RELOAD1G TLB reload LOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA) DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONSData cache misses by locked instructions L1_4K_TLB_HITL1 4K TLB hitL1_2M_TLB_HITL1 2M TLB hitL1_1G_TLB_HITL1 1G TLB hit SW_PREFETCH_HIT_IN_L1Software prefetch hit in the L1.SW_PREFETCH_HIT_IN_L2Software prefetch hit in L2. NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memoryCACHE_DISABLEDRequests to cache-disabled (CD) memorySTREAMING_STOREStreaming store (SS) requests CANCELLEDCancelled prefetchesATTEMPTEDPrefetch attempts DATA_ERRORData Error OCTWORD_WRITE_TRANSFEROctword write transfer INSTRUCTIONSIC fillDATADC fillTLB_WALKTLB fill (page table walks)SNOOPTag snoop requestCancelled requestHW_PREFETCH_FROM_DCHardware prefetch from DC ? DC fill (includes possible replays, whereas EventSelect 041h does not)TLB page table walk L2_FILLSL2 fills (victims from L1 caches, TLB page table walks and data prefetches)L2_WRITEBACKSL2 Writebacks to system. 4K_PAGE_FETCHESInstruction fetches to a 4K page.2M_PAGE_FETCHESInstruction fetches to a 2M page. INVALIDATING_PROBE_NO_IN_FLIGHTInvalidating probe that did not hit any in-flight instructions.INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHTInvalidating probe that hit one or more in-flight instructions.SMC_NO_INFLIGHTSMC that did not hit any in-flight instructions.SMC_INFLIGHTSMC that hit one or more in-flight instructions. X87X87 instructionsMMX_AND_3DNOWMMX and 3DNow! instructionsSSE_AND_SSE2SSE and SSE2 instructions FIXED_AND_LPAFixed and LPALPASMINMIINITSTARTUPINTEOI @ STOPGRANTSHUTDOWNWBINVDINVD X87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtraps DCT0_HITDCT0 Page hitDCT0_MISSDCT0 Page MissDCT0_CONFLICTDCT0 Page ConflictDCT1_PAGE_HITDCT1 Page hitDCT1_PAGE_MISSDCT1 Page MissDCT1_PAGE_CONFLICTDCT1 Page ConflictWRITE_REQUESTWrite request.READ_REQUESTRead request. @ PAGE_TABLE_OVERFLOWPage Table OverflowSTALE_TABLE_ENTRY_HITSNumber of stale table entry hits. (hit on a page closed too soon).PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTEDPage table idle cycle limit incremented.PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTEDPage table idle cycle limit decremented.PAGE_TABLE_CLOSED_INACTIVITYPage table is closed due to row inactivity. DCT0_RBDDCT0 RBD.DCT1_RBDDCT1 RBD.DCT0_PREFETCHDCT0 Prefetch.DCT1_PREFETCHDCT1 Prefetch. @ DCT0_READ_TO_WRITEDCT0 read-to-write turnaround.DCT0_WRITE_TO_READDCT0 write-to-read turnaroundDCT1_READ_TO_WRITEDCT1 read-to-write turnaround.DCT1_WRITE_TO_READDCT1 write-to-read turnaround COUNTER_REACHEDD18F2x[1,0]94[DcqBypassMax] counter reached.BANK_CLOSEDBank is closed due to bank conflict with an outstanding request in the RBD queue. MEMHOT_L_ASSERTIONSMEMHOT_L assertions.HTC_TRANSITIONSNumber of times the HTC transitions from inactive to active.CLOCKS_HTC_P_STATE_INACTIVENumber of clocks HTC P-state is inactive.CLOCKS_HTC_P_STATE_ACTIVENumber of clocks HTC P-state is activePROCHOT_L_ASSERTIONSPROCHOT_L asserted by an external source and the assertion causes a P-state change. @ I_O_TO_I_OIO to IOI_O_TO_MEMIO to MemCPU_TO_I_OCPU to IOCPU_TO_MEMCPU to Mem VICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSRead Block (Dcache load miss refill)SHARED_ICACHE_REFILLRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)READ_TO_DIRTYChange-to-Dirty (first store to clean block already in cache) = NON_POSTED_WRITE_BYTENon-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytesNON_POSTED_WRITE_DWORDNon-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORDPOSTED_WRITE_BYTEPosted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPOSTED_WRITE_DWORDPosted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesREAD_BYTE_4_BYTESSzRd Byte (4 bytes) Legacy or mapped IOREAD_DWORD_1_16_DWORDSSzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size ? MISSProbe missHIT_CLEANProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_HIGH_PRIORITY_READSUpstream high priority reads.UPSTREAM_LOW_PRIORITY_READSUpstream low priority reads.UPSTREAM_LOW_PRIORITY_WRITESUpstream low priority writes. DEV_HITDEV hitDEV_MISSDEV missDEV_ERRORDEV error @p 32_BYTES_WRITES32 Bytes Sized Writes64_BYTES_WRITES64 Bytes Sized Writes32_BYTES_READS32 Bytes Sized Reads64_BYTES_READS64 Byte Sized Reads @x GUEST_LARGERGuest page size is larger than the host page size.MTRR_MISMATCHMTRR mismatch.HOST_LARGERHost page size is larger than the guest page size. ADD_SUB_OPSAdd/subtract opsMUL_OPSMultiply opsDIV_OPSDivide ops DISPATCHED_FPUDispatched FPU OperationsCYCLES_NO_FPU_OPS_RETIREDCycles in which the FPU is EmptyDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsRETIRED_SSE_OPERATIONSRetired SSE OperationsRETIRED_MOVE_OPSRetired Move OpsRETIRED_SERIALIZING_OPSRetired Serializing OpsFP_SCHEDULER_CYCLESNumber of Cycles that a Serializing uop is in the FP SchedulerSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitLS_BUFFER_2_FULL_CYCLESLS Buffer 2 FullLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsCANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONSCancelled Store to Load Forward OperationsSMIS_RECEIVEDSMIs ReceivedDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or NorthbridgeDATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from the NorthbridgeDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITL1 DTLB Miss and L2 DTLB HitL1_DTLB_AND_L2_DTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesMICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESSMicroarchitectural Late Cancel of an AccessMICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESSMicroarchitectural Early Cancel of an AccessPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsL1_DTLB_HITL1 DTLB HitINEFFECTIVE_SW_PREFETCHESIneffective Software PrefetchesGLOBAL_TLB_FLUSHESGlobal TLB FlushesMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHESData PrefetcherNORTHBRIDGE_READ_RESPONSESNorthbridge Read Responses by Coherency StateOCTWORDS_WRITTEN_TO_SYSTEMOctwords Written to SystemCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackPAGE_SIZE_MISMATCHESPage Size MismatchesINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsINSTRUCTION_CACHE_LINES_INVALIDATEDInstruction Cache Lines InvalidatedITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB Reloads AbortedRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_AND_FP_INSTRUCTIONSRetired MMX/FP InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_BRANCH_ABORTDispatch Stall for Branch Abort to RetireDISPATCH_STALL_FOR_SERIALIZATIONDispatch Stall for SerializationDISPATCH_STALL_FOR_SEGMENT_LOADDispatch Stall for Segment LoadDISPATCH_STALL_FOR_REORDER_BUFFER_FULLDispatch Stall for Reorder Buffer FullDISPATCH_STALL_FOR_RESERVATION_STATION_FULLDispatch Stall for Reservation Station FullDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FPU FullDISPATCH_STALL_FOR_LS_FULLDispatch Stall for LS FullDISPATCH_STALL_WAITING_FOR_ALL_QUIETDispatch Stall Waiting for All QuietDISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNCDispatch Stall for Far Transfer or Resync to RetireFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesRETIRED_X87_OPSRetired x87 Floating Point OperationsLFENCE_INST_RETIREDLFENCE Instructions RetiredSFENCE_INST_RETIREDSFENCE Instructions RetiredMFENCE_INST_RETIREDMFENCE Instructions RetiredDRAM_ACCESSES_PAGEDRAM AccessesMEMORY_CONTROLLER_0_PAGEDRAM Controller 0 Page Table EventsMEMORY_CONTROLLER_SLOT_MISSESMemory Controller DRAM Command Slots MissedMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_RBD_QUEUEMemory Controller RBD Queue EventsMEMORY_CONTROLLER_1_PAGEDRAM Controller 1 Page Table EventsTHERMAL_STATUSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsPROBEProbe Responses and Upstream RequestsDEVDEV EventsMEMORY_CONTROLLER_REQUESTSMemory Controller RequestsSIDEBAND_SIGNALSSideband Signals and Special CyclesInterrupt Events !"#$&'*+@ABCDEFGHIKLMRTeglmv}~e  AMD64 Fam12h Llanoamd64_fam12h_llanoint^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4    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JXtXsize_tamd64_fam12h_thermal_statussizetypeamd64_fam12h_data_prefetchesamd64_fam12h_data_cache_refills_from_northbridgeamd64_fam12h_memory_controller_turnaroundsvalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONE_IO_save_endPFM_PMU_AMD64amd64_fam12h_segment_register_loadsPFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_baseamd64_fam12h_cache_blockPFM_PMU_AMD64_FAM14H_BOBCATamd64_fam12h_octwords_written_to_systemPFM_PMU_ARM_CORTEX_A15amd64_fam12h_requests_to_l2PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEamd64_fam12h_ineffective_sw_prefetchesnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong intPFM_PMU_MAXpme_countPFM_PMU_MIPS_34Kamd64_fam12h_instruction_cache_lines_invalidated_IO_markerPFM_PMU_AMD64_K8_REVBPFM_PMU_AMD64_K8_REVCPFM_PMU_AMD64_K8_REVDPFM_PMU_AMD64_K8_REVEPFM_PMU_AMD64_K8_REVFPFM_PMU_AMD64_K8_REVGPFM_PMU_INTEL_SNBEP_UNC_QPI0PFM_PMU_INTEL_SNBEP_UNC_QPI1ngrpPFM_DTYPE_MAXamd64_fam12h_retired_x87_opspfm_event_info_tPFM_PMU_PPC970amd64_fam12h_retired_serializing_opsPFM_PMU_INTEL_SNBEP_UNC_CB0signed charPFM_PMU_INTEL_SNBEP_UNC_CB2PFM_PMU_INTEL_SNBEP_UNC_CB3PFM_PMU_INTEL_SNBEP_UNC_CB4PFM_PMU_INTEL_SNBEP_UNC_CB5PFM_PMU_INTEL_SNBEP_UNC_CB6PFM_PMU_INTEL_SNBEP_UNC_CB7_IO_FILEamd64_fam12h_cpu_io_requests_to_memory_ioos_datapmu_terminateunsigned charPFM_PMU_INTEL_KNCPFM_ATTR_CTRL_PMUPFM_ATTR_CTRL_MAXctrlamd64_fam12h_llano_supportPFM_PMU_MIPS_R10000PFM_PMU_INTEL_SNBEP_UNC_R2PCIEamd64_fam12h_pepfm_pmu_tPFM_PMU_MIPS_R12000charmodelamd64_fam12h_retired_mmx_and_fp_instructionsdfl_plmPFM_PMU_AMD64_FAM10H_BARCELONApfmlib_pmu_tPFM_PMU_POWER5pname_IO_lock_tamd64_fam12h_fpu_exceptionsPFM_PMU_MIPS_ICE9APFM_PMU_MIPS_ICE9BPFM_ATTR_MOD_INTEGERPFM_PMU_SPARC_ULTRA3PLUSflags_IO_read_ptrattrsPFM_PMU_MIPS_5KCamd64_fam12h_memory_controller_page_table_events_posamd64_fam12h_interrupt_eventsPFM_PMU_TORRENTPFM_PMU_INTEL_SNBEP_UNC_IMC0PFM_PMU_INTEL_SNBEP_UNC_IMC1PFM_PMU_INTEL_SNBEP_UNC_IMC2PFM_PMU_INTEL_SNBEP_UNC_IMC3_markersamd64_fam12h_fp_scheduler_cyclesPFM_ATTR_MAXPFM_PMU_MIPS_VR5432pfm_event_attr_info_tdfl_val64amd64_fam12h_cancelled_store_to_load_forward_operationsPFM_DTYPE_RATIOamd64_umask_tnumasks_offsetPFM_PMU_INTEL_SNBEP_UNC_R3QPI0PFM_PMU_INTEL_SNBEP_UNC_R3QPI1PFM_PMU_POWER3PFM_PMU_POWER4PFM_PMU_POWER5PFM_PMU_POWER6PFM_PMU_POWER7PFM_PMU_POWER8PFM_PMU_ARM_1176PFM_PMU_CELLpfm_pmu_type_tamd64_fam12h_data_cache_refillsPFM_PMU_AMD64_FAM10H_SHANGHAIuflagslong unsigned intmax_encodingamd64_fam12h_locked_ops_flags2_IO_read_baseget_event_nextamd64_fam12h_prefetch_instructions_dispatchedthis_unused2pfm_amd64_cfgPFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescpfm_amd64_config_tPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000amd64_fam12h_dram_accesses_pagepfm_dtype_tamd64_fam12h_l2_cache_missPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPamd64_fam12h_memory_controller_requestsPFM_PMU_I386_P6PFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64PFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunamePFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSPFM_PMU_SPARC_NIAGARA1_IO_write_endPFM_PMU_INTEL_PPROumasksnpattrscountdfl_booleventamd64_fam12h_l1_itlb_miss_and_l2_itlb_miss_IO_buf_baseunsigned intPFM_PMU_SPARC_ULTRA3amd64_entry_t__pad1__pad2__pad3__pad4__pad5_sbufamd64_fam12h_retired_sse_operationsis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsPFM_PMU_S390X_CPUM_CF_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstramd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hitpfmlib_pmuPFM_PMU_TYPE_COREPFM_PMU_INTEL_NHMamd64_fam12h_memory_controller_slot_missesPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMamd64_fam12h_l1_dtlb_hitamd64_fam12h_memory_requestssteppingcan_auto_encodeget_event_attr_infosizerevisionlong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12amd64_fam12h_l2_fill_writebackPFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3amd64_fam12h_data_cache_lines_evicted_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descamd64_fam12h_page_size_mismatchesPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_COREamd64_fam12h_dcache_misses_by_locked_instructionsamd64_fam12h_retired_move_ops_next__off64_tcodeamd64_fam12h_devdtypepfmlib_amd64_fam12h.cget_event_nattrsamd64_modsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWPFM_PMU_SPARC_ULTRA3Iosidamd64_fam12h_northbridge_read_responsesPFM_DTYPE_UINT64amd64_fam12h_memory_rbd_queueshort intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesamd64_fam12h_dispatched_fpuget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetamd64_fam12h_l1_dtlb_and_l2_dtlb_missPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gPFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endmodmskPFM_PMU_INTEL_X86_ARCHPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoamd64_fam12h_probereservedPFM_PMU_INTEL_NHM_EXshort unsigned intpfm_amd64_fam12h_llano_detectdfl_intvalidate_tablepmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2amd64_fam12h_sized_commandsPFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regpfm_os_tsupported_plmpfmlib_event_desc_tamd64_fam12h_sideband_signalsGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx CAC ~ .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @C0+ &01;g 6ȯAHfiC%T|g0b0 {Azv 00-8p< `3Wu `   /`O `@$ @Vo` `@ `<W`v` !`" #;%W& w@)`*+@-` /8@0b 2{5 8`9:;<" T2C   Pao3Jfpfmlib_amd64_fam12h.camd64_fam12h_dispatched_fpuamd64_fam12h_retired_sse_operationsamd64_fam12h_retired_move_opsamd64_fam12h_retired_serializing_opsamd64_fam12h_fp_scheduler_cyclesamd64_fam12h_segment_register_loadsamd64_fam12h_locked_opsamd64_fam12h_cancelled_store_to_load_forward_operationsamd64_fam12h_data_cache_refillsamd64_fam12h_data_cache_refills_from_northbridgeamd64_fam12h_data_cache_lines_evictedamd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hitamd64_fam12h_l1_dtlb_and_l2_dtlb_missamd64_fam12h_prefetch_instructions_dispatchedamd64_fam12h_dcache_misses_by_locked_instructionsamd64_fam12h_l1_dtlb_hitamd64_fam12h_ineffective_sw_prefetchesamd64_fam12h_memory_requestsamd64_fam12h_data_prefetchesamd64_fam12h_northbridge_read_responsesamd64_fam12h_octwords_written_to_systemamd64_fam12h_requests_to_l2amd64_fam12h_l2_cache_missamd64_fam12h_l2_fill_writebackamd64_fam12h_l1_itlb_miss_and_l2_itlb_missamd64_fam12h_instruction_cache_lines_invalidatedamd64_fam12h_retired_mmx_and_fp_instructionsamd64_fam12h_interrupt_eventsamd64_fam12h_sideband_signalsamd64_fam12h_fpu_exceptionsamd64_fam12h_dram_accesses_pageamd64_fam12h_memory_controller_page_table_eventsamd64_fam12h_memory_controller_slot_missesamd64_fam12h_memory_controller_turnaroundsamd64_fam12h_memory_rbd_queueamd64_fam12h_thermal_statusamd64_fam12h_cpu_io_requests_to_memory_ioamd64_fam12h_cache_blockamd64_fam12h_sized_commandsamd64_fam12h_probeamd64_fam12h_devamd64_fam12h_memory_controller_requestsamd64_fam12h_page_size_mismatchesamd64_fam12h_retired_x87_opsamd64_fam12h_pepfm_amd64_fam12h_llano_detectpfm_amd64_detectpfm_amd64_cfgamd64_fam12h_llano_supportamd64_modspfm_amd64_get_event_firstpfm_amd64_get_event_nextpfm_amd64_get_event_infopfm_amd64_get_event_nattrspfm_amd64_event_is_validpfm_amd64_get_event_attr_infopfm_amd64_get_encodingpfm_amd64_get_perf_encodingpfm_amd64_perf_validate_pattrspfm_amd64_validate_table<(=gg@ TH?Ph@pAxBCDEFGGHHI9H~ (@@HX`}h (@H` h8Zi}7P p(@H`}h B` }( @ X ( @ }H  ` ` c c f f i i l  l o ( o @ r H r ` }h        ( ( @ { H  ` }h   (  @  H  `  h  } ` h     3?} (07>HRX^g }(  ((@0H7`>hHRX^g@P} .<JXf}`h*8F}@H` h"&} (@}H`n| }(@Xy}  (0@VHh`h} (@}H>H^g07RX`k }(@W}`h 1E }(@1E }(@P }(@Pr}   @     1 @ !}!! !!$!!5!!C!!_!!l!"}"`" "h".""<""<""@""@""D""D""H""H"#M"#M" #U"(#U"@#Y"H#Y"`#}h#############$#$# $}($%@$%X$ %p$(%$@%$H%$`%$h%$%}%&%&%&%&%&%&%'%'% ' &('&@'+&H'>&`'Q&h'_&'n&'{&'}'@)'H)'`)'h)()H()p()()()()))})`**h* ******&**4**C**Q**}*++++,7+,J+ ,h+(,+@,+H,+`,}h,@-,H-,`-,h-,-}- /-(/-@/-H/-`/.h/@./j././././}/@0/H0/`0/h0/0 000000)00}0 20(20@2 1H2 1`2E1h2`1212121212}252525C35`353535=45P46464 65(6 5@6}H6 8`6(8e6@8p6H8z6`86h8686878h787878787879}9`9 9h9(99099999B99L99}9:9:9:::::,::;::P::_:;};; ;;0;<c;<q; <;(<;@<}H<<`<<l<<}<<<=<=< =}(= T@=(TO=0TPTi=XT=T=T=T=T>TT>T+>TU<>UT> U@Ul>HU>PU pU>xU>U U>U ?UP?Ux?V?V?0V?8V?@V `V?hV?V@V5@VP@V@V V@V@ W@(W@PW@XWAWAW(AW`WXAWxAWWAWAW XAXA X@X BHX%BPX`pX>BxXRBXhBXBXBXBY(CYPCY@0YxC8YC@Y `YChYCpYYCYCYYDY+DY>DYNDZ  ZfD(ZvD0ZPZDXZD`ZZDZDZZ EZEZ3EZBEZ`[WE[eE [@[uEH[EP[p[Ex[E[;[E[E[E[F\0F\XF0\F8\F`\Fh\F\G\&G\\HG\G\G\G ]G(]GP]HX]H]3H]MH]hH]H] ]H]H^H^H@^HH^ Ip^"Ix^/I^ 8 E 8 L 8S 8oa 8Vf 8q 8~ 8# 8 8 8@ 8 8 8 8 8v 8 8 8  8  8 8& ) 8 6 8C 8P 8] 8j 8w 8e 8I 8  8  8} 8 8  8X 8  8  8  8  8  8 - 8: 8; H 8TO 8[ 8g 8 s 8* 8 8  8  8 8$ 8 8^  8 8  8 8  8r 84 " 8F( 8. 8"4 8m: 8=@ 8F 8SL 8<R 8X 8u^ 8d 8cj 8rp 8v 8R | 8  8 8  8  8{ 8 8 8K  86 8  8 8 8= 8  8/ 8 8n  8  8  8  8? 8  8  8d  8 8 8 8,$ 8* 80 86 8< 8B 80H 8N 8 T 8+[ 8b 8i 8Mp 8=w 8~ 8  8 8H 8V 8w 8 8k 8 8 8 8 8 8 89 8U 8q 8 8 8 8]  8z 8 8 8& 8F- 8c4 8+; 8B 8 I 8 P 8W 8}^ 8: e 8! l 8s 8Kz 8e 8 8 8+  8_ 8 8 8 8_ 83 8 8X  8 8  8n 8 8 8 8 8! 8@' 8- 8l3 89 8t ? 8WE 8L 8 _ 8e 8.k 8q 8@x 8 8 8f  8M 8 8 8  8 8O 8/ 8^  82 81 8K 8X 8dl 8 8 8  8 82  85 8\  8 8O 8/ 8^ 82) 86 8P 8Rj 8 ~ 8O 8/ 8 8  8 8  8' 8  8e  8N + 87 8C 8V O 8[ 8gh 8u 8 8 8 8/ 8O 8 8k 8 8 8 8 8 8! 88 8yD 8P 8 \ 8h 8t 8 8 8 8s 8 8 8c 8 8 8 8 8tA 8 82 8 8x 8 8 8 8  8O! 8/- 8G 9 8E 8 Q 8] 8 i 8 8 87 8 8 8 8~ 8  C 86  8*H 8 Tr 8~ 8 8  8  8   8<  > 8g J`X 8Ies 8  8 8` 8 @ 8   8% 82@ 8M [ 8,hv 8 8 8` 8  8L 8k  8% 3 8@!^ 8/k`"y 8# 8_% 8 & 8@) 84`* 8z + 8Q(@-6 8C /Q 8^@0l 8y 2 8 5 8Q 8 8`9 86 : 84; 8<9 8F TT 8W`>i 8D  8( 4Q /858 1386324441 1009 1009 100664 64632 ` ELF>@@UHH H}HEHE}tEE}EuER PIPE0Pipe 0 (fadd, imul, mmx) opsPIPE1Pipe 1 (fmul, store, mmx) opsANYPipe 1 and Pipe 0 ops SINGLE_ADD_SUB_OPSSingle precision add/subtract opsSINGLE_MUL_OPSSingle precision multiply opsSINGLE_DIV_OPSSingle precision divide/square root opsDOUBLE_ADD_SUB_OPSDouble precision add/subtract opsDOUBLE_MUL_OPSDouble precision multiply opsDOUBLE_DIV_OPSDouble precision divide/square root opsOP_TYPEOp type: 0=uops. 1=FLOPSALLAll sub-events selected @ ALL_OTHER_MERGING_MOVE_UOPSAll other merging move uopsALL_OTHER_MOVE_UOPSAll other move uops SSE_BOTTOM_EXECUTING_UOPSSSE bottom-executing uops retiredSSE_BOTTOM_SERIALIZING_UOPSSSE bottom-serializing uops retiredX87_BOTTOM_EXECUTING_UOPSX87 bottom-executing uops retiredX87_BOTTOM_SERIALIZING_UOPSX87 bottom-serializing uops retired ADD_SUB_OPSAdd/substract opsMULT_OPSMultiply opsDIV_FSQRT_OPSDivide and fqsrt ops ESCSSSDSFSGSHS @ EXECUTEDNumber of locked instructions executedBUS_LOCKNumber of cycles to acquire bus lockUNLOCK_LINENumber of cycles to unlock line (not including cache miss) ADDRESS_MISMATCHESAddress mismatches (starting byte not the same).STORE_IS_SMALLER_THAN_LOADStore is smaller than load.MISALIGNEDMisaligned. UNCACHEABLEFrom non-cacheable dataSHAREDFrom shared linesEXCLUSIVEFrom exclusive linesOWNEDFrom owned linesMODIFIEDFrom modified lines Uncacheable dataSharedExclusiveOwnedModified PROBEEviction from probeShared evictionExclusive evictionOwned evictionModified eviction STORES_L1TLB_MISSStores that miss L1TLBLOADS_L1TLB_MISSLoads that miss L1TLBSTORES_L2TLB_MISSStores that miss L2TLBLOADS_L2TLB_MISSLoads that miss L2TLB LOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA) L1_4K_TLB_HITL1 4K TLB hitL1_2M_TLB_HITL1 2M TLB hit HITSW prefetch hit in the data cachePENDING_FILLSW prefetch hit a pending fillNO_MABSW prefetch does not get a MABL2_HITSW prefetch hits L2 NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memorySTREAMING_STOREStreaming store (SS) requests DC_BUFFER_0Data cache buffer 0DC_BUFFER_1Data cache buffer 1DC_BUFFER_2Data cache buffer 2DC_BUFFER_3Data cache buffer 3DC_BUFFER_4Data cache buffer 4DC_BUFFER_5Data cache buffer 5DC_BUFFER_6Data cache buffer 6DC_BUFFER_7Data cache buffer 7IC_BUFFER_0Instruction cache Buffer 1IC_BUFFER_1Instructions cache buffer 1ANY_IC_BUFFERAny instruction cache bufferANY_DC_BUFFERAny data cache buffer   DATA_ERRORData ErrorDIRTY_SUCCESSChange-to-dirty successUncacheable @ INSTRUCTIONSIC fillDATADC fillSNOOPTag snoop request DC fill (includes possible replays, whereas EventSelect 041h does not) L2_FILLSL2 fills (victims from L1 caches, TLB page table walks and data prefetches)L2_WRITEBACKSL2 Writebacks to system.IC_ATTR_WRITES_L2_ACCESSIc attribute writes which access the L2IC_ATTR_WRITES_L2_WRITESIc attribute writes which store into the L2 4K_PAGE_FETCHESInstruction fetches to a 4K page.2M_PAGE_FETCHESInstruction fetches to a 2M page. INVALIDATING_LS_PROBEIC invalidate due to an LS probeINVALIDATING_BU_PROBEIC invalidate due to a BU probe X87X87 or MMX instructionsSSESSE (SSE, SSE2, SSE3, MNI) instructions X87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtraps DCT0 Page hitMISSDCT0 Page MissCONFLICTDCT0 Page ConflictWRITE_REQUESTWrite request@G DCT0_PAGE_TABLE_OVERFLOWDCT0 Page Table OverflowDCT0_PAGE_TABLE_STALE_HITDCT0 number of stale table entry hits (hit on a page closed too soon)DCT0_PAGE_TABLE_IDLE_INCDCT0 page table idle cycle limit incrementedDCT0_PAGE_TABLE_IDLE_DECDCT0 page table idle cycle limit decrementedDCT0_PAGE_TABLE_CLOSEDDCT0 page table is closed due to row inactivity DCT0_RBDDCT0 RBDDCT0_PREFETCHDCT0 prefetch@P DCQ_BYPASS_MAXDCQ_BYPASS_MAX counter reachedBANK_CLOSEDBank is closed due to bank conflict with an outstanding request in the RBD queue MEMHOT_LMEMHOT_L assertionsHTC_TRANSITIONNumber of times HTC transitions from inactive to activeCLOCKS_HTC_P_STATE_INACTIVENumber of clocks HTC P-state is inactive.CLOCKS_HTC_P_STATE_ACTIVENumber of clocks HTC P-state is activePROCHOT_LPROCHOT_L asserted by an external source and the assertion causes a P-state change @ I_O_TO_I_OIO to IOI_O_TO_MEMIO to MemCPU_TO_I_OCPU to IOCPU_TO_MEMCPU to Mem VICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSRead Block (Dcache load miss refill)SHARED_ICACHE_REFILLRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)CHANGE_TO_DIRTYChange-to-Dirty (first store to clean block already in cache) = NON_POSTED_WRITE_BYTENon-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytesNON_POSTED_WRITE_DWORDNon-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORDPOSTED_WRITE_BYTEPosted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPOSTED_WRITE_DWORDPosted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesREAD_BYTE_4_BYTESSzRd Byte (4 bytes) Legacy or mapped IOREAD_DWORD_1_16_DWORDSSzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size ? Probe missHIT_CLEANProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_HIGH_PRIO_READSUpstream high priority readsUPSTREAM_LOW_PRIO_READSUpstream low priority readsUPSTREAM_LOW_PRIO_WRITESUpstream non-ISOC writes DEV hitDEV missERRORDEV error @p 32_BYTES_WRITES32 Bytes Sized Writes64_BYTES_WRITES64 Bytes Sized Writes32_BYTES_READS32 Bytes Sized Reads64_BYTES_READS64 Byte Sized Reads @x STOPGRANTStopgrantSHUTDOWNShutdownWBINVDWbinvdINVDInvd FIXED_AND_LPAFixed and LPALPASMINMIINITSTARTUPINTEOI @ HOST_PDE_LEVELHost PDE levelHOST_PDPE_LEVELHost PDPE levelHOST_PML4E_LEVELHost PML4E levelGUEST_PDE_LEVELGuest PDE levelGUEST_PDPE_LEVELGuest PDPE levelGUEST_PML4E_LEVELGuest PML4E level @g DISPATCHED_FPUNumber of uops dispatched to FPU execution pipelinesCYCLES_NO_FPU_OPS_RETIREDCycles in which the FPU is EmptyDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsRETIRED_SSE_OPERATIONSRetired SSE OperationsRETIRED_MOVE_OPSRetired Move OpsRETIRED_SERIALIZING_OPSRetired Serializing OpsRETIRED_X87_FPU_OPSNumber of x87 floating points ops that have retiredSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitRSQ_FULLNumber of cycles that the RSQ holds retired stores. This buffer holds the stores waiting to retired as well as requests that missed the data cacge and waiting on a refillLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsCANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONSCancelled Store to Load Forward OperationsDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or NorthbridgeDATA_CACHE_REFILLS_FROM_NBData Cache Refills from the NorthbridgeDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITNumber of data cache accesses that miss in the L1 DTLB and hit the L2 DTLB. This is a speculative eventDTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsL1_DTLB_HITL1 DTLB HitDCACHE_SW_PREFETCHESNumber of software prefetches that do not cuase an actual data cache refillGLOBAL_TLB_FLUSHESGlobal TLB FlushesMEMORY_REQUESTSMemory Requests by TypeMAB_REQUESTSNumber of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_WAIT_CYCLES.MAB_WAIT_CYCLESLatency of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_REQUESTS.SYSTEM_READ_RESPONSESNorthbridge Read Responses by Coherency StateCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsINSTRUCTION_CACHE_LINES_INVALIDATEDInstruction Cache Lines InvalidatedITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB Reloads AbortedRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_FLOATING_POINT_INSTRUCTIONSRetired SSE/MMX/FP InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesDRAM_ACCESSES_PAGEDRAM AccessesMEMORY_CONTROLLER_PAGE_TABLENumber of page table events in the local DRAM controllerMEMORY_CONTROLLER_SLOT_MISSESMemory Controller DRAM Command Slots MissedMEMORY_CONTROLLER_RBD_QUEUE_EVENTSMemory Controller Bypass Counter SaturationTHERMAL_STATUSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsProbe Responses and Upstream RequestsDEV_EVENTSDEV EventsMEMORY_CONTROLLER_REQUESTSMemory Controller RequestsSIDEBAND_SIGNALS_SPECIAL_SIGNALSSideband signals and special cyclesINTERRUPT_EVENTSInterrupt eventsPDC_MISSPDC miss !"#$&'*@ABCDEFGKLMRTeh i lv}~ bAMD64 Fam14h Bobcatamd64_fam14h_bobcatTint^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4       !; "; #; $ 0 &u ' ( )u  *; +; ,; -;$ .;({   /  8     H I JW KW LW  M #EW^$EX%retEWl  n {&  ^   {& . & R ^   {& b    {& z & 5 & O & i   ~ {& ړ n&  n'  n' . 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JXtXsize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEAMD64_FAM10H_REV_BAMD64_FAM10H_REV_CAMD64_FAM10H_REV_Damd64_fam14h_cpu_io_requests_to_memory_io_IO_save_endPFM_PMU_AMD64amd64_fam14h_retired_floating_point_instructionsPFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2amd64_fam14h_dispatched_fpuPFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainamd64_fam14h_retired_serializing_opsPFM_DTYPE_DOUBLE_cur_columnivalPFM_PMU_MIPS_25KFamd64_fam14h_dev_eventsamd64_fam14h_prefetch_instructions_dispatchedPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong 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unsigned intmax_encodingamd64_fam14h_dcache_sw_prefetches_flags2_IO_read_baseget_event_nextthis_unused2pfm_amd64_cfgPFM_PMU_MIPS_RM7000PFM_OS_PERF_EVENTudescpfm_amd64_config_tPFM_PMU_MIPS_VR5500PFM_PMU_MIPS_RM9000pfm_dtype_tPFM_ATTR_UMASK_old_offsetucodePFM_PMU_INTEL_IVB_EPPFM_PMU_I386_P6amd64_fam14h_retired_x87_fpu_opsPFM_PMU_PPC970MPos_detectsvalPFM_PMU_GEN_IA64amd64_fam14h_data_cache_refillsPFM_PMU_I386_PMlong long intpfmlib_attr_desc_tunameamd64_fam14h_pdc_missPFM_PMU_ITANIUMpmu_initPFM_PMU_AMD64_FAM15H_INTERLAGOSAMD64_K8_REV_BPFM_PMU_SPARC_NIAGARA1_IO_write_endPFM_PMU_INTEL_PPROumasksamd64_fam14h_fpu_exceptionsamd64_fam14h_segment_register_loadsnpattrscountdfl_boolevent_IO_buf_baseamd64_fam14h_dram_accesses_pageunsigned intPFM_PMU_SPARC_ULTRA3amd64_entry_tamd64_fam14h_instruction_cache_lines_invalidated__pad1__pad2__pad3__pad4__pad5_sbufamd64_fam14h_data_cache_lines_evictedis_precisePFM_PMU_INTEL_SNBEP_UNC_UBOXPFM_PMU_AMD64_FAM12H_LLANOget_event_encoding_flagsPFM_PMU_S390X_CPUM_CFamd64_fam14h_l2_fill_writeback_modepfm_attr_ctrl_tPFM_PMU_COREDUOfamilyPFM_PMU_INTEL_WSM_UNCfstrAMD64_CPU_UNamd64_fam14h_l2_cache_misspfmlib_pmuPFM_PMU_TYPE_COREamd64_fam14h_cache_blockPFM_PMU_INTEL_NHMPFM_PMU_TYPE_UNCOREevent_is_validget_num_eventsamd64_fam14h_mab_requestsnum_fixed_cntrsPFM_ATTR_CTRL_UNKNOWNFILEPFM_PMU_INTEL_ATOMamd64_fam14h_retired_move_opssteppingcan_auto_encodeget_event_attr_infosizerevisionlong long unsigned intPFM_DTYPE_CHAR8pattrsPFM_ATTR_MOD_BOOLPFM_PMU_INTEL_WSM_DP__off_tPFM_PMU_INTEL_NETBURSTPFM_DTYPE_INT64PFM_DTYPE_UNKNOWNPFM_PMU_TYPE_MAXPFM_PMU_ARM_CORTEX_A8PFM_PMU_ARM_CORTEX_A9perf_nameis_dflPFM_PMU_MONTECITOPFM_PMU_SPARC_ULTRA12PFM_PMU_INTEL_SNB_UNC_CB0PFM_PMU_INTEL_SNB_UNC_CB1PFM_PMU_INTEL_SNB_UNC_CB2PFM_PMU_INTEL_SNB_UNC_CB3_IO_backup_base_shortbufPFM_PMU_INTEL_SNBEP_UNC_CB1descPFM_PMU_AMD64_FAM11H_TURIONPFM_PMU_INTEL_CORE_next__off64_tcodedtypeget_event_nattrsamd64_modsPFM_PMU_TYPE_OS_GENERICPFM_PMU_INTEL_IVB_UNC_CB0PFM_PMU_INTEL_IVB_UNC_CB1_IO_buf_endPFM_PMU_INTEL_IVB_UNC_CB2PFM_PMU_INTEL_IVB_UNC_CB3PFM_ATTR_RAW_UMASKpfmlib_amd64_fam14h.cPFM_PMU_INTEL_NETBURST_PPFM_PMU_INTEL_HSWamd64_fam14h_bobcat_supportPFM_PMU_SPARC_ULTRA3IosidPFM_DTYPE_UINT64short intatdescPFM_PMU_INTEL_WSMpmu_detectuint64_tgrpidcodesget_event_first/home/reissman/papi-5.3.0/src/libpfm4/lib_vtable_offsetPFM_PMU_INTEL_SNBGNU C 4.7.2 20120921 (Red Hat 4.7.2-2) -fpreprocessed -mtune=generic -march=x86-64 -gamd64_fam14h_pePFM_PMU_INTEL_SNBEP_UNC_HApfm_attr_treserved_bitsamd64_fam14h_sideband_signals_special_signalsPFM_PMU_INTEL_SNBEP_UNC_PCUPFM_OS_MAX_IO_read_endmodmskAMD64_FAM14H_REV_BPFM_PMU_INTEL_X86_ARCHAMD64_K8_REV_CPFM_PMU_AMD64_FAM10H_ISTANBUL_filenoamd64_fam14h_retired_sse_operationsreservedPFM_PMU_INTEL_NHM_EXshort unsigned intdfl_intvalidate_tableAMD64_K7pmu_rev_IO_write_ptrPFM_PMU_INTEL_SNB_EPPFM_DTYPE_FIXEDnum_cntrsPFM_PMU_ITANIUM2PFM_PMU_MIPS_24KPFM_OS_PERF_EVENT_EXTPFM_PMU_MIPS_74Kdisplay_regamd64_fam14h_memory_controller_rbd_queue_eventspfm_os_tsupported_plmpfmlib_event_desc_tGCC: (GNU) 4.7.2 20120921 (Red Hat 4.7.2-2)zRx CAC ~ .symtab.strtab.shstrtab.rela.text.rela.data.bss.rela.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @C0+ &1;HW 609HXXC8%T@lg\n0b0 {nzvH 0p0-8` x7 `3`W`u@@ / O w `` ` :Tw` @` `)`Zv ! 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L 3S 3Fa 34f 3^q 3~ 3 3 3 3  3 3t 3 3 32 3 3 3j  3 3 3z ) 3 6 3jC 3P 3}] 3j 3{ w 3 3> 3b  3%  3< 3 3 3O 3/  3 3 3 3  3- 3n: 3 H 3-O 3[ 3g 3s 3 3. 3  3  3 3 3 3L  3f 3  3 3  3 3 " 3=( 3. 34 3s: 3@ 3F 3L 3R 3MX 3S^ 3d 38j 3p 3v 3 | 3  3 3  3  38 3K 3 3  3 39 3 3 3 3c  3  3| 3}  3u  3  3  3 3  3  3[  3W 3I 3 3$ 3* 30 36 3< 3B 3H 3N 3 T 3 [ 3b 3i 3p 3w 3~ 34  3 3 3 3n 3 3 3/ 3I 3c 3 3 3 3  3& 3B 3^ 3z 3J 3  3$  3A  3^  3& 3- 3;4 3; 3AB 37 I 3V P 3#W 39^ 3 e 37 l 3s 36z 3P 3v 3 3  3= 3` 3 3 3& 3 3 3  3  3  37 3 3 3  3e 3! 35' 3}- 3+3 39 3 ? 3 E 3]L 3 _ 3e 35k 3q 3Gx 3t 3 3  3" 3 3 3 3p 3( 3 3U  3 31 3K 3X 3jl 3k 3 3 3p 3  3 3  3 3( 3 3U 3) 36 3P 3j 3 ~ 3( 3 3 3  3H 3  3 3 3  3 + 37 30C 3 O 3[ 30h 3u 3 3 3 3 3( 3 3I 33 3 3 3 3r 3! 38 3PD 3iP 3+ \ 3h 3t 3x 3 3 3: 3 3 3 3 3 3 3I 3IA 3 3  3 3 31 3 3} 3  3(! 3- 3 9 3E 3' Q 3] 3i 3X 3N 3 3 3T 3 3^ 3m 3| 3 3; 3N 3a 3 3 3 3  3 3 ! 3+3CB 3 o 3!{ 3F` 3 3@ 3\ @! 3 -; 3)GU 3ja  3   3  3  3` 3w` 3  3@ , : 3Ge 3Xr 3 3  3 3O  3d@ 3\ " 3/= 3 JX 3 es 3 ! 3 " 3U # 3$ 3t& 3'% 32@+@ 3wM-[ 3_h/v 3  0 3~1 3Y1 3 3 3:G 3)92 3 H 3 /Q /881 1386324441 1009 1009 100664 94624 ` ELF>@@UHH H}HEHE}tEE}FuFrOPS_PIPE0Total number uops assigned to Pipe 0OPS_PIPE1Total number uops assigned to Pipe 1OPS_PIPE2Total number uops assigned to Pipe 2OPS_PIPE3Total number uops assigned to Pipe 3OPS_DUAL_PIPE0Total number dual-pipe uops assigned to Pipe 0OPS_DUAL_PIPE1Total number dual-pipe uops assigned to Pipe 1OPS_DUAL_PIPE2Total number dual-pipe uops assigned to Pipe 2OPS_DUAL_PIPE3Total number dual-pipe uops assigned to Pipe 3ALLAll sub-events selected @ SINGLE_ADD_SUB_OPSSingle-precision add/subtract FLOPSSINGLE_MUL_OPSSingle-precision multiply FLOPSSINGLE_DIV_OPSSingle-precision divide/square root FLOPSSINGLE_MUL_ADD_OPSSingle precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSDOUBLE_ADD_SUB_OPSDouble precision add/subtract FLOPSDOUBLE_MUL_OPSDouble precision multiply FLOPSDOUBLE_DIV_OPSDouble precision divide/square root FLOPSDOUBLE_MUL_ADD_OPSDouble precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS @ SSE_MOVE_OPSNumber of SSE Move OpsSSE_MOVE_OPS_ELIMNumber of SSE Move Ops eliminatedOPT_CANDNumber of Ops that are candidates for optimization (Z-bit set or pass)SCALAR_OPS_OPTIMIZEDNumber of Scalar ops optimized SSE_RETIREDSSE bottom-executing uops retiredSSE_MISPREDICTEDSSE control word mispredict traps due to mispredictionsX87_RETIREDX87 bottom-executing uops retiredX87_MISPREDICTEDX87 control word mispredict traps due to mispredictions ESCSSSDSFSGSHS @ LOAD_QUEUEThe number of cycles that the load buffer is fullSTORE_QUEUEThe number of cycles that the store buffer is full EXECUTEDNumber of locked instructions executedCYCLES_NON_SPECULATIVE_PHASENumber of cycles spent in non-speculative phase, excluding cache miss penaltyCYCLES_WAITINGNumber of cycles spent in non-speculative phase, including the cache miss penalty SIZE_ADDRESS_MISMATCHESStore is smaller than load or different starting byte but partial overlap DC_MISS_STREAMING_STOREFirst data cache miss or streaming store to a 64B cache lineSTREAMING_STOREFirst streaming store to a 64B cache line GOODFill with good data. (Final valid status is valid)INVALIDEarly valid status turned out to be invalidPOISONFill with poison dataREAD_ERRORFill with read data error 4K_DATA4 KB unified TLB hit for data2M_DATA2 MB unified TLB hit for data1G_DATA1 GB unified TLB hit for data4K_INST4 KB unified TLB hit for instruction2M_INST2 MB unified TLB hit for instruction1G_INST1 GB unified TLB hit for instruction @w 4 KB unified TLB miss for data2 MB unified TLB miss for data1GB_DATA1 GB unified TLB miss for data4 KB unified TLB miss for instruction2 MB unified TLB miss for instruction1 GB unified TLB miss for instruction @w LOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA) SW_PREFETCH_HIT_IN_L1Software prefetch hit in the L1SW_PREFETCH_HIT_IN_L2Software prefetch hit in the L2 NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to non-cacheable (WC, but not WC+/SS) memoryRequests to non-cacheable (WC+/SS, but not WC) memory ATTEMPTEDPrefetch attempts BUFFER_BIT_0Buffer entry index bit 0BUFFER_BIT_1Buffer entry index bit 1BUFFER_BIT_2Buffer entry index bit 2BUFFER_BIT_3Buffer entry index bit 3BUFFER_BIT_4Buffer entry index bit 4BUFFER_BIT_5Buffer entry index bit 5BUFFER_BIT_6Buffer entry index bit 6BUFFER_BIT_7Buffer entry index bit 7 @ EXCLUSIVEExclusiveMODIFIEDModified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)SHAREDSharedOWNEDOwnedDATA_ERRORData ErrorMODIFIED_UNWRITTENModified unwritten ? OCTWORD_WRITE_TRANSFEROW write transfer INSTRUCTIONSIC fillDATADC fillTLB_WALKTLB fill (page table walks)SNOOPNB probe requestCANCELLEDCanceled requestPREFETCHERL2 cache prefetcher request@_ DC fill (includes possible replays, whereas PMCx041 does not)TLB page table walkL2 Cache Prefetcher request L2_FILLSL2 fills from systemL2_WRITEBACKSL2 Writebacks to system (Clean and Dirty)L2_WRITEBACKS_CLEANL2 Clean Writebacks to system GUEST_LARGERGuest page size is larger than host page size when nested paging is enabledMTRR_MISMATCHSplintering due to MTRRs, IORRs, APIC, TOMs or other special address regionHOST_LARGERHost page size is larger than the guest page size 4K_PAGE_FETCHESInstruction fetches to a 4 KB page2M_PAGE_FETCHESInstruction fetches to a 2 MB page1G_PAGE_FETCHESInstruction fetches to a 1 GB page NON_SMC_PROBE_MISSNon-SMC invalidating probe that missed on in-flight instructionsNON_SMC_PROBE_HITNon-SMC invalidating probe that hit on in-flight instructionsSMC_PROBE_MISSSMC invalidating probe that missed on in-flight instructionsSMC_PROBE_HITSMC invalidating probe that hit on in-flight instructions X87X87 instructionsMMXMMX(tm) instructionsSSESSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4) TOTAL_FAULTSTotal microfaultsTOTAL_TRAPSTotal microtrapsINT2EXT_FAULTSInt2Ext faultsEXT2INT_FAULTSExt2Int faultsBYPASS_FAULTSBypass faults TAGGEDNumber of ops tagged by IBSRETIREDNumber of ops tagged by IBS that retiredIGNOREDNumber of times an op could not be tagged by IBS because of a previous tagged op that has not retired LOADSLoadsSTORESStoresLOAD_OP_STORESLoad-op-Stores LOAD_L1_MISS_SEEN_BY_PREFETCHERLoad L1 miss seen by prefetcherSTORE_L1_MISS_SEEN_BY_PREFETCHERStore L1 miss seen by prefetcher DCT0_PAGE_HITDCT0 Page hitDCT0_PAGE_MISSDCT0 Page MissDCT0_PAGE_CONFLICTDCT0 Page ConflictDCT1_PAGE_HITDCT1 Page hitDCT1_PAGE_MISSDCT1 Page MissDCT1_PAGE_CONFLICTDCT1 Page Conflict ? DCT0_PAGE_TABLE_OVERFLOWDCT0 Page Table OverflowDCT1_PAGE_TABLE_OVERFLOWDCT1 Page Table Overflow DCT0_COMMAND_SLOTS_MISSEDDCT0 Command Slots Missed (in MemClks)DCT1_COMMAND_SLOTS_MISSEDDCT1 Command Slots Missed (in MemClks) DCT0_DIMM_TURNAROUNDDCT0 DIMM (chip select) turnaroundDCT0_READ_WRITE_TURNAROUNDDCT0 Read to write turnaroundDCT0_WRITE_READ_TURNAROUNDDCT0 Write to read turnaroundDCT1_DIMM_TURNAROUNDDCT1 DIMM (chip select) turnaroundDCT1_READ_WRITE_TURNAROUNDDCT1 Read to write turnaroundDCT1_WRITE_READ_TURNAROUNDDCT1 Write to read turnaround ? MEMORY_CONTROLLER_HIGH_PRIORITY_BYPASSMemory controller high priority bypassMEMORY_CONTROLLER_MEDIUM_PRIORITY_BYPASSMemory controller medium priority bypassDCT0_DCQ_BYPASSDCT0 DCQ bypassDCT1_DCQ_BYPASSDCT1 DCQ bypass NUM_HTC_TRIP_POINT_CROSSEDNumber of times the HTC trip point is crossedNUM_CLOCKS_HTC_PSTATE_INACTIVENumber of clocks HTC P-state is inactiveNUM_CLOCKS_HTC_PSTATE_ACTIVENumber of clocks HTC P-state is active @d REMOTE_IO_TO_LOCAL_IORemote IO to Local IOREMOTE_CPU_TO_LOCAL_IORemote CPU to Local IOLOCAL_IO_TO_REMOTE_IOLocal IO to Remote IOLOCAL_IO_TO_REMOTE_MEMLocal IO to Remote MemLOCAL_CPU_TO_REMOTE_IOLocal CPU to Remote IOLOCAL_CPU_TO_REMOTE_MEMLocal CPU to Remote MemLOCAL_IO_TO_LOCAL_IOLocal IO to Local IOLOCAL_IO_TO_LOCAL_MEMLocal IO to Local MemLOCAL_CPU_TO_LOCAL_IOLocal CPU to Local IOLOCAL_CPU_TO_LOCAL_MEMLocal CPU to Local MemadVICTIM_BLOCKVictim Block (Writeback)READ_BLOCKRead Block (Dcache load miss refill)READ_BLOCK_SHAREDRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)CHANGE_TO_DIRTYChange-to-Dirty (first store to clean block already in cache) = NON-POSTED_SZWR_BYTENon-Posted SzWr Byte (1-32 bytes). Typical Usage: Legacy or mapped IO, typically 1-4 bytes.NON-POSTED_SZWR_DWNon-Posted SzWr DW (1-16 dwords). Typical Usage: Legacy or mapped IO, typically 1POSTED_SZWR_BYTEPosted SzWr Byte (1-32 bytes). Typical Usage: Subcache-line DMA writes, size varies; alsoPOSTED_SZWR_DWPosted SzWr DW (1-16 dwords). Typical Usage: Block-oriented DMA writes, often cache-lineSZRD_BYTESzRd Byte (4 bytes). Typical Usage: Legacy or mapped IO.SZRD_DWSzRd DW (1-16 dwords). Typical Usage: Block-oriented DMA reads, typically cache-line size. ? PROBE_MISSProbe missPROBE_HIT_CLEANProbe hit cleanPROBE_HIT_DIRTY_WITHOUT_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)PROBE_HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_DISPLAY_REFRESH_ISOC_READSUpstream display refresh/ISOC readsUPSTREAM_NON-DISPLAY_REFRESH_READSUpstream non-display refresh readsUPSTREAM_ISOC_WRITESUpstream ISOC writesUPSTREAM_NON-ISOC_WRITESUpstream non-ISOC writes @ GART_APERTURE_HIT_ON_ACCESS_FROM_CPUGART aperture hit on access from CPUGART_APERTURE_HIT_ON_ACCESS_FROM_IOGART aperture hit on access from IOGART_MISSGART missGART_REQUEST_HIT_TABLE_WALK_IN_PROGRESSGART Request hit table walk in progressGART_MULTIPLE_TABLE_WALK_IN_PROGRESSGART multiple table walk in progress COMMAND_DW_SENTCommand DW sentDATA_DW_SENTData DW sentBUFFER_RELEASE_DW_SENTBuffer release DW sentNOP_DW_SENTNOP DW sent (idle)ADDRESS_DW_SENTAddress (including extensions) DW sentPER_PACKET_CRC_SENTPer packet CRC sentSUBLINK_1When links are unganged, enable this umask to select sublink 1SUBLINK_0When links are unganged, enable this umask to select sublink 0 (default when links ganged) ?  LOCAL_TO_NODE_0From Local node to Node 0LOCAL_TO_NODE_1From Local node to Node 1LOCAL_TO_NODE_2From Local node to Node 2LOCAL_TO_NODE_3From Local node to Node 3LOCAL_TO_NODE_4From Local node to Node 4LOCAL_TO_NODE_5From Local node to Node 5LOCAL_TO_NODE_6From Local node to Node 6LOCAL_TO_NODE_7From Local node to Node 7 @  @ READ_BLOCK_LOCAL_TO_NODE_0Read block From Local node to Node 0READ_BLOCK_SHARED_LOCAL_TO_NODE_0Read block shared From Local node to Node 0READ_BLOCK_MODIFIED_LOCAL_TO_NODE_0Read block modified From Local node to Node 0CHANGE_TO_DIRTY_LOCAL_TO_NODE_0Change-to-Dirty From Local node to Node 0READ_BLOCK_LOCAL_TO_NODE_1Read block From Local node to Node 1READ_BLOCK_SHARED_LOCAL_TO_NODE_1Read block shared From Local node to Node 1READ_BLOCK_MODIFIED_LOCAL_TO_NODE_1Read block modified From Local node to Node 1CHANGE_TO_DIRTY_LOCAL_TO_NODE_1Change-to-Dirty From Local node to Node 1READ_BLOCK_LOCAL_TO_NODE_2Read block From Local node to Node 2READ_BLOCK_SHARED_LOCAL_TO_NODE_2Read block shared From Local node to Node 2READ_BLOCK_MODIFIED_LOCAL_TO_NODE_2Read block modified From Local node to Node 2CHANGE_TO_DIRTY_LOCAL_TO_NODE_2Change-to-Dirty From Local node to Node 2READ_BLOCK_LOCAL_TO_NODE_3Read block From Local node to Node 3READ_BLOCK_SHARED_LOCAL_TO_NODE_3Read block shared From Local node to Node 3READ_BLOCK_MODIFIED_LOCAL_TO_NODE_3Read block modified From Local node to Node 3CHANGE_TO_DIRTY_LOCAL_TO_NODE_3Change-to-Dirty From Local node to Node 3!"$(ABDH READ_BLOCK_LOCAL_TO_NODE_4Read block From Local node to Node 4READ_BLOCK_SHARED_LOCAL_TO_NODE_4Read block shared From Local node to Node 4READ_BLOCK_MODIFIED_LOCAL_TO_NODE_4Read block modified From Local node to Node 4CHANGE_TO_DIRTY_LOCAL_TO_NODE_4Change-to-Dirty From Local node to Node 4READ_BLOCK_LOCAL_TO_NODE_5Read block From Local node to Node 5READ_BLOCK_SHARED_LOCAL_TO_NODE_5Read block shared From Local node to Node 5READ_BLOCK_MODIFIED_LOCAL_TO_NODE_5Read block modified From Local node to Node 5CHANGE_TO_DIRTY_LOCAL_TO_NODE_5Change-to-Dirty From Local node to Node 5READ_BLOCK_LOCAL_TO_NODE_6Read block From Local node to Node 6READ_BLOCK_SHARED_LOCAL_TO_NODE_6Read block shared From Local node to Node 6READ_BLOCK_MODIFIED_LOCAL_TO_NODE_6Read block modified From Local node to Node 6CHANGE_TO_DIRTY_LOCAL_TO_NODE_6Change-to-Dirty From Local node to Node 6READ_BLOCK_LOCAL_TO_NODE_7Read block From Local node to Node 7READ_BLOCK_SHARED_LOCAL_TO_NODE_7Read block shared From Local node to Node 7READ_BLOCK_MODIFIED_LOCAL_TO_NODE_7Read block modified From Local node to Node 7CHANGE_TO_DIRTY_LOCAL_TO_NODE_7Change-to-Dirty From Local node to Node 7!"$(ABDH READ_SIZED_LOCAL_TO_NODE_0Read Sized From Local node to Node 0WRITE_SIZED_LOCAL_TO_NODE_0Write Sized From Local node to Node 0VICTIM_BLOCK_LOCAL_TO_NODE_0Victim Block From Local node to Node 0READ_SIZED_LOCAL_TO_NODE_1Read Sized From Local node to Node 1WRITE_SIZED_LOCAL_TO_NODE_1Write Sized From Local node to Node 1VICTIM_BLOCK_LOCAL_TO_NODE_1Victim Block From Local node to Node 1READ_SIZED_LOCAL_TO_NODE_2Read Sized From Local node to Node 2WRITE_SIZED_LOCAL_TO_NODE_2Write Sized From Local node to Node 2VICTIM_BLOCK_LOCAL_TO_NODE_2Victim Block From Local node to Node 2READ_SIZED_LOCAL_TO_NODE_3Read Sized From Local node to Node 3WRITE_SIZED_LOCAL_TO_NODE_3Write Sized From Local node to Node 3VICTIM_BLOCK_LOCAL_TO_NODE_3Victim Block From Local node to Node 3READ_SIZED_LOCAL_TO_NODE_4Read Sized From Local node to Node 4WRITE_SIZED_LOCAL_TO_NODE_4Write Sized From Local node to Node 4VICTIM_BLOCK_LOCAL_TO_NODE_4Victim Block From Local node to Node 4READ_SIZED_LOCAL_TO_NODE_5Read Sized From Local node to Node 5WRITE_SIZED_LOCAL_TO_NODE_5Write Sized From Local node to Node 5VICTIM_BLOCK_LOCAL_TO_NODE_5Victim Block From Local node to Node 5READ_SIZED_LOCAL_TO_NODE_6Read Sized From Local node to Node 6WRITE_SIZED_LOCAL_TO_NODE_6Write Sized From Local node to Node 6VICTIM_BLOCK_LOCAL_TO_NODE_6Victim Block From Local node to Node 6READ_SIZED_LOCAL_TO_NODE_7Read Sized From Local node to Node 7WRITE_SIZED_LOCAL_TO_NODE_7Write Sized From Local node to Node 7VICTIM_BLOCK_LOCAL_TO_NODE_7Victim Block From Local node to Node 7ALL_LOCAL_TO_NODE_0_3All From Local node to Node 0-3ALL_LOCAL_TO_NODE_4_7All From Local node to Node 4-7!"$ABD)*,IJL PROBE_HIT_SProbe Hit SPROBE_HIT_EProbe Hit EPROBE_HIT_MUW_OR_OProbe Hit MuW or OPROBE_HIT_MProbe Hit MProbe MissDIRECTED_PROBEDirected ProbeTRACK_CACHE_STAT_FOR_RDBLKTrack Cache Stat for RdBlkTRACK_CACHE_STAT_FOR_RDBLKSTrack Cache Stat for RdBlkS @ TRACK_CACHE_STAT_FOR_CHGTODIRTYTrack Cache Stat for ChgToDirtyTRACK_CACHE_STAT_FOR_RDBLKMTrack Cache Stat for RdBlkM @ WRITE_REQUESTS_TO_DCTWrite requests sent to the DCTREAD_REQUESTS_TO_DCTRead requests (including prefetch requests) sent to the DCTPREFETCH_REQUESTS_TO_DCTPrefetch requests sent to the DCT32_BYTES_SIZED_WRITES32 Bytes Sized Writes64_BYTES_SIZED_WRITES64 Bytes Sized Writes32_BYTES_SIZED_READS32 Bytes Sized Reads64_BYTE_SIZED_READS64 Byte Sized ReadsREAD_REQUESTS_TO_DCT_WHILE_WRITES_PENDINGRead requests sent to the DCT while writes requests are pending in the DCT @ READ_BLOCK_EXCLUSIVERead Block Exclusive (Data cache read)Read Block Shared (Instruction cache read)READ_BLOCK_MODIFYRead Block ModifyPREFETCHCount prefetches honlyREAD_BLOCK_ANYCount any read requestCORE_0Measure on Core0CORE_1Measure on Core1CORE_2Measure on Core2CORE_3Measure on Core3CORE_4Measure on Core4CORE_5Measure on Core5CORE_6Measure on Core6CORE_7Measure on Core7ANY_COREMeasure on any core  0@P`p Modified  0@P`p  L3_REQUEST_CYCLEL3 Request cycle count.L3_REQUESTL3 request count. DISPATCHED_FPU_OPSFPU Pipe AssignmentCYCLES_FPU_EMPTYFP Scheduler EmptyRETIRED_SSE_OPSRetired SSE/BNI OpsMOVE_SCALAR_OPTIMIZATIONNumber of Move Elimination and Scalar Op OptimizationRETIRED_SERIALIZING_OPSRetired Serializing OpsBOTTOM_EXECUTE_OPNumber of Cycles that a Bottom-Execute uop is in the FP SchedulerSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitLOAD_Q_STORE_Q_FULLLoad Queue/Store Queue FullLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsCANCELLED_STORE_TO_LOADCanceled Store to Load Forward OperationsSMIS_RECEIVEDSMIs ReceivedDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGEData Cache Refills from L2 or SystemDATA_CACHE_REFILLS_FROM_NORTHBRIDGEData Cache Refills from SystemUNIFIED_TLB_HITUnified TLB HitUNIFIED_TLB_MISSUnified TLB MissMISALIGNED_ACCESSESMisaligned AccessesPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedINEFFECTIVE_SW_PREFETCHESIneffective Software PrefetchesMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHERData PrefetcherMAB_REQSMAB RequestsMAB_WAITMAB Wait CyclesSYSTEM_READ_RESPONSESResponse From System on Cache RefillsOCTWORD_WRITE_TRANSFERSOctwords Written to SystemCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_CACHE_FILL_WRITEBACKL2 Fill/WritebackPAGE_SPLINTERINGPage SplinteringINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss, L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss, L2 ITLB MissPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsINSTRUCTION_CACHE_INVALIDATEDInstruction Cache Lines InvalidatedITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB Reloads AbortedRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_FP_INSTRUCTIONSRetired MMX/FP InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_SERIALIZATIONMicrosequencer Stall due to SerializationDISPATCH_STALL_FOR_RETIRE_QUEUE_FULLDispatch Stall for Instruction Retire Q FullDISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULLDispatch Stall for Integer Scheduler Queue FullDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FP Scheduler Queue FullDISPATCH_STALL_FOR_LDQ_FULLDispatch Stall for LDQ FullMICROSEQ_STALL_WAITING_FOR_ALL_QUIETMicrosequencer Stall Waiting for All QuietFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINTSDR0 Breakpoint MatchDR1_BREAKPOINTSDR1 Breakpoint MatchDR2_BREAKPOINTSDR2 Breakpoint MatchDR3_BREAKPOINTSDR3 Breakpoint MatchIBS_OPS_TAGGEDTagged IBS OpsLS_DISPATCHLS DispatchEXECUTED_CLFLUSH_INSTRUCTIONSExecuted CLFLUSH InstructionsL2_PREFETCHER_TRIGGER_EVENTSL2 Prefetcher Trigger EventsDISPATCH_STALL_FOR_STQ_FULLDispatch Stall for STQ FullDRAM_ACCESSESDRAM AccessesDRAM_CONTROLLER_PAGE_TABLE_OVERFLOWSDRAM Controller Page Table OverflowsMEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSEDMemory Controller DRAM Command Slots MissedMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_BYPASS_COUNTER_SATURATIONMemory Controller Bypass Counter SaturationTHERMAL_STATUSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCK_COMMANDSCache Block CommandsSIZED_COMMANDSSized CommandsPROBE_RESPONSES_AND_UPSTREAM_REQUESTSProbe Responses and Upstream RequestsGART_EVENTSGART EventsLINK_TRANSMIT_BANDWIDTH_LINK_0Link Transmit Bandwidth Link 0LINK_TRANSMIT_BANDWIDTH_LINK_1Link Transmit Bandwidth Link 1LINK_TRANSMIT_BANDWIDTH_LINK_2Link Transmit Bandwidth Link 2LINK_TRANSMIT_BANDWIDTH_LINK_3Link Transmit Bandwidth Link 3CPU_TO_DRAM_REQUESTS_TO_TARGET_NODECPU to DRAM Requests to Target NodeIO_TO_DRAM_REQUESTS_TO_TARGET_NODEIO to DRAM Requests to Target NodeCPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3CPU Read Command Latency to Target Node 0-3CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3CPU Read Command Requests to Target Node 0-3CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7CPU Read Command Latency to Target Node 4-7CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7CPU Read Command Requests to Target Node 4-7CPU_COMMAND_LATENCY_TO_TARGET_NODECPU Command Latency to Target NodeCPU_REQUESTS_TO_TARGET_NODECPU Requests to Target NodeREQUEST_CACHE_STATUS_0Request Cache Status 0REQUEST_CACHE_STATUS_1Request Cache Status 1MEMORY_CONTROLLER_REQUESTSMemory Controller RequestsREAD_REQUEST_TO_L3_CACHERead Request to L3 CacheL3_CACHE_MISSESL3 Cache MissesL3_FILLS_CAUSED_BY_L2_EVICTIONSL3 Fills caused by L2 EvictionsL3_EVICTIONSL3 EvictionsNON_CANCELED_L3_READ_REQUESTSNon-canceled L3 Read RequestsL3_LATENCYL3 Latency   !"#$&'*+@ABCEFGKRegh i lmv}~e)0l           AMD64 Fam15h Interlagosamd64_fam15h_interlagosint^^B8B1GW (08@ H!P"X$`&h(Wp,Wt.ex243I48ApJKLMNPWR     WN  {G  {WC      !"#$%&'()*+,-./0123456789:;<=>?ΨKwV12;3;@&k'()*+ pmu,(-K,idx.W0/W40W8<5@A;B;C;EFGHWIW@7i89:;< =(idx>W,?w0w48K5 6 7 89u@AB>id?WDPS pmuT UW VW WW XW Y ZW [ ] ^ (_0 (`H e f g hpmui jW kW lW$ mW( nW, oW0 pW4 r8pesK @ uR H w] P x] X yn ` z] h { p | x } ~    @ f  ]    {?i 0 { @ {aQ !X "n c W Wt W W k ; W W WW W WW  : {W4 4 @  ` P {"` 4 P ] v {W  v " 4       !; "; #; $ 0 &u ' ( )u  *; +; ,; -;$ .;({   /  H I JW KW LW  M #EW $EX%retEWl   {& c2  & L    a {& v Q& ː Q   {&     {'     {'    % {' +; ' 7V ' Gq Q   {' _ v'  v'  '  '  ' # ' >  ' Y v' +t ' 7 v' W Q' o '  '  '  Q' 1   F {' \ 6' w '  '  ' + v' K ' [ ' k v' 4 Q' O   d { ' z T'  6'  v' (  ' P 6' l  '   ' 7    L {' b <' I} <   {'  ' &  ' N  ' v     { ' $ ' ? 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JXtXamd64_fam15h_l3_evictionssize_tsizetypevalidate_pattrsPFM_ATTR_NONEPFM_PMU_NONEamd64_fam15h_read_request_to_l3_cache_IO_save_endPFM_PMU_AMD64amd64_fam15h_l3_latencyamd64_fam15h_l2_cache_missPFM_PMU_MIPS_SB1_IO_write_basePFM_PMU_SPARC_NIAGARA2PFM_PMU_INTEL_PII_lockequivPFM_PMU_PERF_EVENTPFM_PMU_INTEL_IVBtype_IO_save_basePFM_PMU_AMD64_FAM14H_BOBCATPFM_PMU_ARM_CORTEX_A15PFM_PMU_AMD64_K7PFM_PMU_INTEL_NHM_UNCPFM_PMU_MIPS_20KC_chainamd64_fam15h_cpu_io_requests_to_memory_ioPFM_DTYPE_DOUBLE_cur_columnamd64_fam15h_memory_controller_bypass_counter_saturationivalPFM_PMU_MIPS_25KFPFM_ATTR_CTRL_PERF_EVENTget_event_infoPFM_OS_NONEamd64_fam15h_memory_requestsnattrsPFM_PMU_TYPE_UNKNOWNPFM_PMU_POWERPCpfmlib_attr_tdfl_strPFM_PMU_SPARC_ULTRA4PLUSlong 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